MT4C4M4A1TG-6S
Abstract: MT4LC4M4B1TG-6S
Text: 4 MEG x 4 FPM DRAM MT4LC4M4B1, MT4C4M4B1 MT4LC4M4A1, MT4C4M4A1 DRAM For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View • Industry-standard x4 pinout, timing, functions,
|
Original
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: 4 MEG x 4 FPM DRAM TECHNOLOGY, INC. MT4LC4M4B1, MT4C4M4B1 MT4LC4M4A1, MT4C4M4A1 DRAM FEATURES • Industry-standard x4 pinout, timing, functions and packages • State-of-the-art, high-performance, low power CMOS silicon-gate process • Single power supply +3.3V ±0.3V or +5V ±10%
|
Original
|
PDF
|
24/26-Pin
NC/A11
|
Untitled
Abstract: No abstract text available
Text: OBSOLETE 4 MEG x 4 FPM DRAM MT4LC4M4B1, MT4C4M4B1 MT4LC4M4A1, MT4C4M4A1 DRAM For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View • Industry-standard x4 pinout, timing, functions,
|
Original
|
PDF
|
|
D49 MARKING
Abstract: No abstract text available
Text: 4 MEG x 4 FPM DRAM MT4LC4M4B1, MT4C4M4B1 MT4LC4M4A1, MT4C4M4A1 DRAM For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View • Industry-standard x4 pinout, timing, functions,
|
Original
|
PDF
|
|
MT4LC1M16C3
Abstract: No abstract text available
Text: OBSOLETE 1, 2, 4 MEG x 32 DRAM SODIMMs MT2LDT132H X (S), MT4LDT232H(X)(S), MT8LDT432H(X)(S) SMALL-OUTLINE DRAM MODULE For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES • JEDEC pinout in a 72-pin, small-outline, dual in-line
|
Original
|
PDF
|
MT2LDT132H
MT4LDT232H
MT8LDT432H
72-pin,
024-cycle
048-cycle
MT4LC1M16C3
|
Untitled
Abstract: No abstract text available
Text: PRELIMINARY MT4LD T 164A (X), MT8LD264A (X), MT16LD464A (X) 1, 2, 4 MEG x 64 DRAM MODULES TECHNOLOGY, INC. 1, 2, 4 MEG x 64 DRAM MODULE 8, 16, 32 MEGABYTE, NONBUFFERED, 3.3V, EDO OR FAST PAGE MODE FEATURES • • • • • • • • • • PIN ASSIGNMENT (Front View)
|
Original
|
PDF
|
MT8LD264A
MT16LD464A
168-Pin
168-pin,
024-cycle
048-cycle
|
diode marking u34
Abstract: No abstract text available
Text: ADVANCE MT36LD872A X 8 MEG x 72 DRAM MODULE DRAM MODULE 8 MEG x 72 64 MEGABYTE, ECC, NONBUFFERED, 3.3V, 8 CAS#, FAST PAGE OR EDO PAGE MODE FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • JEDEC- and industry-standard eight CAS#, ECC pinout in a 168-pin, dual-in-line memory module
|
Original
|
PDF
|
MT36LD872A
168-Pin
168-pin,
276mW
048-cycle
diode marking u34
|
MT18LD472A
Abstract: MT9LD272A
Text: PRELIMINARY MT9LD272A X , MT18LD472A(X) 2, 4 MEG x 72 DRAM MODULES TECHNOLOGY, INC. DRAM MODULE 2, 4 MEG x 72 16, 32 MEGABYTE, ECC, NONBUFFERED, 3.3V, 8 CAS#, FAST PAGE OR EDO PAGE MODE FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • Eight CAS#, ECC pinout in a 168-pin, dual-in-line
|
Original
|
PDF
|
MT9LD272A
MT18LD472A
168-Pin
168-pin,
240mW
048-cycle
|
4c4m4a
Abstract: Y7A MARKING
Text: 4 MEG X 4 FPM DRAM I^ IIC R C IN MT4LC4M4B1,MT4C4M4B1 MT4LC4M4A1,MT4C4M4A1 n R AM ^ r » »1 FEATURES • Industry-standard x4 pinout, timing, functions and packages • State-of-the-art, high-performance, low power CMOS silicon-gate process • Single power supply +3.3V ±0.3V or +5V ±10%
|
OCR Scan
|
PDF
|
24/26-Pin
4c4m4a
Y7A MARKING
|
LN 9297
Abstract: No abstract text available
Text: D24A 16 MEG DRAM DIE I ^ I C R O N DRAM DIE 16 MEG DRAM MT4LC4M4B1D24A, MT4LC4M4E8D24A, MT4LC1M16C3D24A, MT4LC1M16E5D24A FEATURES DIE DATA BASE D24A DIE OUTLINE see page 4 • S in g le 3 .3 V (x4, x l 6 ) p o w e r su p p ly • In d u stry -s ta n d a rd x4, x l 6 tim in g an d fu n c tio n s
|
OCR Scan
|
PDF
|
MT4LC4M4B1D24A,
MT4LC4M4E8D24A,
MT4LC1M16C3D24A,
MT4LC1M16E5D24A
LN 9297
|
Untitled
Abstract: No abstract text available
Text: MT4LC4M4B1 S 4 MEG X 4 DRAM MICRON • TECHNOLOGY, MC. DRAM 4 MEG x 4 DRAM 2K REFRESH, 3.3V, FAST PAGE MODE, OPTIONAL SELF REFRESH FEATURES • JEDEC- and industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process
|
OCR Scan
|
PDF
|
140mW
048-cycle
WT4LC4M481
|
Untitled
Abstract: No abstract text available
Text: MT4LC4M4B1 L 4 MEG X 4 DRAM MICRON 4 MEG x 4 DRAM DRAM 3.3V, FAST PAGE MODE, OPTIONAL EXTENDED REFRESH FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access -6 -7 • Packages Plastic SOJ (300 mil) DJ • Refresh Rate Standard 32ms period
|
OCR Scan
|
PDF
|
128ms
24/26-Pin
|
Untitled
Abstract: No abstract text available
Text: MICRON 4M E Gx4 . FPM DRAM DRAM MT4LC4M4B1, MT4LC4M4A1 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html
|
OCR Scan
|
PDF
|
|
M995
Abstract: No abstract text available
Text: |V |IC Z R O N MT4LC4M4B1 L 4 MEG X 4 DRAM DRAM 4 MEG x 4 DRAM 3.3V, FAST PAGE MODE, OPTIONAL EXTENDED REFRESH FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access -6 -7 • Packages Plastic SOJ (300 mil) DJ • Refresh Rate
|
OCR Scan
|
PDF
|
180mW
048-cycle
24/26-Pin
M995
|
|
|
Untitled
Abstract: No abstract text available
Text: 4 MEG X 4 FPM DRAM MICRON I TECHNOLOGY. INC. MT4LC4M4B1, MT4C4M4B1 MT4LC4M4A1, MT4C4M4A1 DRAM FEATURES • Industry-standard x4 pinout, timing, functions and packages • State-of-the-art, high-perform ance, low pow er CMOS silicon-gate process • Single pow er supply +3.3V +0.3V or +5V +10%
|
OCR Scan
|
PDF
|
24/26-Pin
|
Untitled
Abstract: No abstract text available
Text: M IC R O N » D24A 16 MEG DRAM DIE SEMCQNDUCTDR n c DRAM DIE 16 MEG DRAM MT4C4M4B1D24A, MT4LC4M4B1D24A MT4LC2M8B1D24A, MT4LC1M16C3D24A FEATURES DIE OUTLINE Top View • • • • • • Single 5.0V (x4 only) or 3.3V (x4, x8, xl6) power supply Industry-standard x4, x8, xl6 timing and functions
|
OCR Scan
|
PDF
|
MT4C4M4B1D24A,
MT4LC4M4B1D24A
MT4LC2M8B1D24A,
MT4LC1M16C3D24A
PHYSICAL531
150mm
262x569
134x134
114jim
|
MT4C4M4
Abstract: No abstract text available
Text: 4 MEG X 4 FPM DRAM M IC R O N n RAM MT4LC4M4B1, MT4C4M4B1 MT4LC4M4A1, MT4C4M4A1 U r tM IV I FEATURES • Industry-standard x4 pinout, timing, functions and packages • State-of-the-art, high-performance, low power CMOS silicon-gate process • Single power supply +3.3V ±0.3V or +5V +10%
|
OCR Scan
|
PDF
|
24/26-Pin
MT4C4M4
|
LEA-5T
Abstract: No abstract text available
Text: MT4LC4M4B1 S 4 MEG X 4 DRAM M IC R O N 4 MEG x 4 DRAM DRAM 3.3V, FAST PAGE MODE, OPTIONAL SELF REFRESH FEATURES PIN ASSIGNMENT (Top View) • JEDEC- and industry-standard x4 pinout, timing, functions and packages • High-perform ance CM OS silicon-gate process
|
OCR Scan
|
PDF
|
180mW
048-cycle
24/26-Pin
D15pm5
LEA-5T
|
Untitled
Abstract: No abstract text available
Text: 8 MEG X 64 NONBUFFERED DRAM DIMM MICRON I TECHNOLOGY, INC. MT32LD864A X DRAM MODULE FEA TURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • JEDEC- and industry-standard eight CAS#, ECC pinout in a 168-pin, dual in-line memory module (DIMM) • 64MB (8 Meg x 64)
|
OCR Scan
|
PDF
|
MT32LD864A
168-Pin
168-pin,
048-cycle
DE-23)
|
Untitled
Abstract: No abstract text available
Text: PRELIMINARY M IC Z R O N I _ « MT18LD472 X 4 MEG X 72 DRAM MODULE DRAM 4 MEG x 72 M o n i l i F IV IW U U L t. 32 MEGABYTE, ECC, 3.3V, FAST PAGE OR EDO PAGE MODE FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • JEDEC-standard ECC pinout in a 168-pin, dual-in-line
|
OCR Scan
|
PDF
|
MT18LD472
168-Pin
168-pin,
240mW
048-cycle
|
Untitled
Abstract: No abstract text available
Text: PRELIMINARY MT9LD272A X , MT18LD472A(X) 2, 4 MEG X 72 DRAM MODULES MICRON I TECHNOLOGY, INC. 2, 4 MEG x 72 DRAM MODULE 16, 32 MEGABYTE, ECC, NONBUFFERED, 3.3V, 8 CAS#, FAST PAGE OR EDO PAGE MODE FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • Eight CAS#, ECC pinout in a 168-pin, dual-in-line
|
OCR Scan
|
PDF
|
MT9LD272A
MT18LD472A
168-Pin
168-pin,
240mW
048-cycle
G01SL01
|
Untitled
Abstract: No abstract text available
Text: 0U| 1X6 o |oul |o x U0J3|1/\| ‘9 6 6 1. eo ito u suoiiE o^ioeds io s p n p o jd e B u e ijo o i m 6u e q i s e A ie s e j ‘ ou| ‘À6o|ouLjoej_ u o jo i^ I 96/1.1. ''© y - g w d 09|/\ld SIMIMIQ IW d Q p®J©^nquof\] ZL * 8 ‘t ‘Z y A|uo uo|sj0a a|/\|t?g ,
|
OCR Scan
|
PDF
|
|
WT16LD
Abstract: tc 97101 INTERNAL DIAGRAM OF IC 7476
Text: PRELIMINARY M IC n a iM 1 M T 16LD T 164(S), M T16LD(T)464(X)(S) 1 MEG, 4 MEG X 64 DRAM M OD ULES 1 MEG, 4 MEG x 64 DRAM MODULE 8, 32 MEGABYTE, 3.3V, OPTIONAL SELF REFRESH, FAST PAGE OR EDO PAGE MODE FEATURES • JEDEC- and industry-standard pinout in a 168-pin,
|
OCR Scan
|
PDF
|
T16LD
168-pin,
024-cycle
128ms
048-cycle
MT16LD
WT16LD
tc 97101
INTERNAL DIAGRAM OF IC 7476
|
VG264265B
Abstract: TC5117405CSJ hyundai cross reference guide TC51V16160 Micron 4MX32 EDO SIMM dram cross reference cross reference tc5117800cft SAMSUNG Cross Reference
Text: Cross Reference Guide 1.3. Cross Reference Guide 1.3.1. Cross Reference of 256kxl6 DRAM Vendors\Configuration VIS Hitachi Hyundai Micron Motorola NEC Samsung Toshiba TI 256kxl6, 5V, EDO VG264265B HM514265D HY514264B MT4C16270 N/A PD4244265LE KM416C254D TC5144265D
|
OCR Scan
|
PDF
|
256kxl6
256kxl6,
VG264265B
HM514265D
HY514264B
MT4C16270
uPD4244265LE
KM416C254D
TC5144265D
TC5117405CSJ
hyundai
cross reference guide
TC51V16160
Micron 4MX32 EDO SIMM
dram cross reference
cross reference
tc5117800cft
SAMSUNG Cross Reference
|
