obsolete micron SDRAM
Abstract: 44-PIN MT48LC2M8A1 16MSDR MT48LC2M8A1TG-10S
Text: OBSOLETE 16 MEG: x4, x8 SDRAM MT48LC4M4A1/A2 S - 2 Meg x 4 x 2 banks MT48LC2M8A1/A2 S - 1 Meg x 8 x 2 banks SYNCHRONOUS DRAM For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View
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MT48LC4M4A1/A2
MT48LC2M8A1/A2
44-Pin
PC100-compliant;
096-cycle
16MSDRAMx4x8
obsolete micron SDRAM
MT48LC2M8A1
16MSDR
MT48LC2M8A1TG-10S
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44-PIN
Abstract: MT48LC2M8A1
Text: 16 MEG: x4, x8 SDRAM MT48LC4M4A1/A2 S - 2 Meg x 4 x 2 banks MT48LC2M8A1/A2 S - 1 Meg x 8 x 2 banks SYNCHRONOUS DRAM For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View
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MT48LC4M4A1/A2
MT48LC2M8A1/A2
44-Pin
PC100-compliant;
096-cycle
16MSDRAMx4x8
MT48LC2M8A1
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BA 4916
Abstract: 4416 dram 44-PIN MT48LC2M8A1
Text: 16 MEG: x4, x8 SDRAM SYNCHRONOUS DRAM MT48LC4M4A1/A2 S - 2 Meg x 4 x 2 banks MT48LC2M8A1/A2 S - 1 Meg x 8 x 2 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/datasheets. FEATURES PIN ASSIGNMENT Top View • PC100-compliant; includes CONCURRENT AUTO
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Original
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PDF
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MT48LC4M4A1/A2
MT48LC2M8A1/A2
PC100-compliant;
096-cycle
16MSDRAMx4x8
BA 4916
4416 dram
44-PIN
MT48LC2M8A1
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AN1766
Abstract: MCF5307 TMS664814-10
Text: Order this document by AN1766/D REV 2.0 Semiconductor Products Sector Communications and Advanced Consumer Technologies Group AN1766 Application Note Using the SDRAM Controller on the MCF5307 ColdFire¨ Integrated Microprocessor Dave Lapham Applications Engineering, Imaging & Entertainment Solutions
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AN1766/D
AN1766
MCF5307
MCF5307
AN1766
TMS664814-10
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AN1766
Abstract: MCF5307 TMS664814-10 MT48LC2M8A-10
Text: Back Order this document by AN1766/D REV 1.0 Consumer Systems Group Communications and Advanced Consumer Technologies Group AN1766 Application Note Using the SDRAM Controller on the MCF5307 ColdFire Integrated Microprocessor Dave Lapham Applications Engineering, Imaging Systems Division
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Original
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PDF
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AN1766/D
AN1766
MCF5307
MCF5307
AN1766
TMS664814-10
MT48LC2M8A-10
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sekisui 5760
Abstract: sis950 SiS chipset 486 SEAGATE st51080n Bt848KPF KSV884T4A1A-07 lad1 5vdc SiS chipset SiS301 kingmax usb flash drive
Text: SiS540 Super 7 2D/3D Ultra-AGPTM Single Chipset Content Figure .vi Table. vii
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SiS540
sekisui 5760
sis950
SiS chipset 486
SEAGATE st51080n
Bt848KPF
KSV884T4A1A-07
lad1 5vdc
SiS chipset
SiS301
kingmax usb flash drive
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MT48LC2M8A1-8B
Abstract: 1F27FC04
Text: Freescale Semiconductor Application Note AN2066/D Rev. 1.5, 11/2001 MPC8xx SDRAM Interface Freescale Semiconductor, Inc. Heinz Wrobel Freescale GmbH, Munich Janet Snyder NCSD Applications, Austin Part I Introduction In the long term, Synchronous DRAMs SDRAM offer system designers at least two
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AN2066/D
MT48LC2M8A1-8B
1F27FC04
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MT8LSDT264HG-662C1
Abstract: MT8LSDT264HG-662 SO-DIMM 144-pin
Text: OBSOLETE 2 MEG x 64 SDRAM SODIMM MT8LSDT264H SMALL-OUTLINE SDRAM MODULE For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Front View • JEDEC-standard 144-pin, small-outline, dual in-line
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MT8LSDT264H
144-pin,
MT8LSDT264HG-662C1
MT8LSDT264HG-662
SO-DIMM 144-pin
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zm05
Abstract: micron power resistor zm05 16Mb SDRAM MICRON
Text: OBSOLETE 4 MEG x 32 SDRAM DIMM MT8LSDT432U SYNCHRONOUS DRAM MODULE For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Front View 100-Pin DIMM • JEDEC-standard pinout in a 100-pin, dual in-line
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MT8LSDT432U
100-Pin
100-pin,
zm05
micron power resistor zm05
16Mb SDRAM MICRON
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16Mb SDRAM
Abstract: MT18LSDT472A
Text: OBSOLETE 2, 4 MEG x 72 SDRAM DIMMs MT9LSDT272A, MT18LSDT472A SYNCHRONOUS DRAM MODULE For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Front View • PC100-compliant; includes CONCURRENT AUTO
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MT9LSDT272A,
MT18LSDT472A
PC100-compliant;
168-pin,
16Mb SDRAM
MT18LSDT472A
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MT48LC2M8A1
Abstract: No abstract text available
Text: PRELIMINARY MT48LC4M4A1 S 4 Meg x 4 MT48LC2M8A1 S (2 Meg x 8) SYNCHRONOUS DRAM FEATURES PIN ASSIGNMENT (TOP VIEW) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle
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OCR Scan
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PDF
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096-cycle
MT48LC4M4A1
MT48LC2M8A1
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY MT48LC4M4A1 S 4 Meg x 4 MT48LC2M8A1 S (2 Meg x 8) FEATURES PIN ASSIGNMENT (TOP VIEW) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle
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OCR Scan
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PDF
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MT48LC4M4A1
MT48LC2M8A1
096-cycle
44-Pin
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N41A
Abstract: No abstract text available
Text: 16 MEG: x4, x8 SDRAM MICRON I TECHNOLOGY, INC. MT48LC4M4A1 /A2 S - 2 Meg x 4 x 2 banks MT48LC2M8A1 /A2 S -1 Meg x 8 x 2 banks SYNCHRONOUS DRAM For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html
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OCR Scan
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PDF
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MT48LC4M4A1
MT48LC2M8A1
096-cycle
44-PIN
N41A
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MARKING code CG QU
Abstract: No abstract text available
Text: OBSOLETE 16 MEG: x4, x8 SDRAM MICRON I TECHNOLOGY, INC. MT48LC4M4A1 /A2 S - 2 Meg x 4 x 2 banks MT48LC2M8A1 /A2 S -1 Meg x 8 x 2 banks SYNCHRONOUS DRAM F or the latest data sheet revisions, please refer to the Micron Web site: www.m icron.com/m ti/msp/htm l/datasheet.htm l
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OCR Scan
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PDF
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MT48LC4M4A1
MT48LC2M8A1
096-cycle
MARKING code CG QU
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY 16 MEG: x4, x8 SDRAM MICRON I TECHNOLOGY, INC. SYNCHRONOUS DRAM MT48LC4M4A1 /A2 S - 2 Meg x 4 x 2 banks MT48LC2M8A1 /A2 S -1 Meg x 8 x 2 banks FEATURES • PCIOO-compliant functionality • Fully synchronous; all signals registered on positive
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OCR Scan
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PDF
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MT48LC4M4A1
MT48LC2M8A1
096-cycle
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Untitled
Abstract: No abstract text available
Text: ADVANCE 2, 4 MEG X 64 SDRAM DIMMs MICRON I TECHNOLOGY, INC. SYNCHRONOUS DRAM MODULE MT8LSD T 264A MT16LSD(T)464A FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • JEDEC-standard 168-pin, dual in-line memory module (DIMM) • Utilizes 83 and 100 MHz SDRAM components
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OCR Scan
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PDF
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MT16LSD
168-Pin
168-pin,
DE-25
DE-26
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Untitled
Abstract: No abstract text available
Text: ADVANCED 4 MEG X 32 SDRAM DIMM |U |IC RO N SDRAM MODULE MT8LSD T 432U FEATURES PIN ASSIGNMENT (Front View) 100-Pin DIMM • JEDEC-standard pinout in a 100-pin, dual in-line memory module (DIMM) • 16MB (4 Meg x 32) • Utilizes 100 MHz SDRAM components • Single +3.3V ±0.3V power supply
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OCR Scan
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PDF
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100-Pin
100-pin,
096-cycle
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ZM02
Abstract: No abstract text available
Text: 2’4 M E Gx64 MICRON I SDRAM DIMMs TECHNOLOGY, INC. SYNCHRONOUS li J| li I t IJ | 1 A^IVI IVI MT8LSDT264A, MT16LSDT464A III ^ For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Front View
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OCR Scan
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PDF
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168-pin,
096-cycle
168-PIN
DF-18
DF-28
ZM02
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VG264265B
Abstract: TC5117405CSJ hyundai cross reference guide TC51V16160 Micron 4MX32 EDO SIMM dram cross reference cross reference tc5117800cft SAMSUNG Cross Reference
Text: Cross Reference Guide 1.3. Cross Reference Guide 1.3.1. Cross Reference of 256kxl6 DRAM Vendors\Configuration VIS Hitachi Hyundai Micron Motorola NEC Samsung Toshiba TI 256kxl6, 5V, EDO VG264265B HM514265D HY514264B MT4C16270 N/A PD4244265LE KM416C254D TC5144265D
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OCR Scan
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PDF
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256kxl6
256kxl6,
VG264265B
HM514265D
HY514264B
MT4C16270
uPD4244265LE
KM416C254D
TC5144265D
TC5117405CSJ
hyundai
cross reference guide
TC51V16160
Micron 4MX32 EDO SIMM
dram cross reference
cross reference
tc5117800cft
SAMSUNG Cross Reference
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marking code MOG 8
Abstract: No abstract text available
Text: ADVANCE 2, 4 MEG X 72 SDRAM DIMMs m ic r o n I TEC H N O LO G Y, M C. SYNCHRONOUS DRAM MODULE MT9LSD T 272A MT 18LSD(T)472A FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • JEDEC-standard 168-pin, dual in-line memory module (DIMM) • Utilizes 83 and 100 MHz SDRAM components
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OCR Scan
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PDF
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18LSD
168-pin,
MT18LSD0Q472A]
096-cycle
oTTTTTTTrrn11111111nTrnTTTi
marking code MOG 8
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GKE1
Abstract: EC Bus
Text: M IC R OTECtfJOLNOGY,INC. 2 4 MEGx 64 SDRAM DIMMs I SYNCHRONOUS DRAM MODULE MT8LSD T 264A MT16LSD(T)464A FEATURES PIN ASSIGNMENT (Front View) • JEDEC-standard 168-pin, dual in-line memory module (DIMM) • PClOO-compliant functionality (-10A) • Utilizes 83 MHz, 100 MHz and 125 MHz SDRAM
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OCR Scan
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PDF
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168-pin,
MT16LSD
096-cycle
MT8LSDT264AG)
168-PIN
MT16LSDT464AG)
MT8LSD264AG)
MT16LSD464AG)
GKE1
EC Bus
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marking code 17W
Abstract: ZM marking
Text: OBSOLETE 2, 4 MEG X 72 SDRAM DIMMs MICRON I TECHNOLOGY, INC. MT9LSDT272A, MT18LSDT472A SYNCHRONOUS DRAM MODULE For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Front View
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OCR Scan
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PDF
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168-pin,
096-cycle
168-PIN
DF-24
DF-25
marking code 17W
ZM marking
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Untitled
Abstract: No abstract text available
Text: 2 MEG X 32 SDRAM DIMM MICRON I TECHNOLOGY, INC. MT4LSDT232U SYNCHRONOUS DRAM MODULE For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Front View • JED EC pinout in a 100-pin, dual in-line m em ory
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OCR Scan
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PDF
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MT4LSDT232U
100-pin,
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Untitled
Abstract: No abstract text available
Text: ADVANCE 2, 4 MEG X 72 SDRAM DIMMs MICRON I TECHNOLOGY, INC. SYNCHRONOUS DRAM MODULE MT9LSD T 272A MT18LSD(T)472A FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • JEDEC-standard 168-pin, dual in-line memory module (DIMM) • Utilizes 83 and 100 MHz SDRAM components
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OCR Scan
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PDF
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MT18LSD
168-Pin
168-pin,
DE-27
DE-28
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