P8251A
Abstract: P82C51A tmp8251 82C51A P8251
Text: T O S H IB A TM P82C51A TMP82C51AP-2 /TMP82C51AP-10 TMP82C51 AM-2/TMP82C51 AM-10 PROGRAM M ABLE COMMUNICATION INTERFACE 1. GENERAL DESCRIPTION T he TM P82C51A is th e in d u stry sta n d a rd U n iv ersa l S ynchron o u s/A sy n ch ro n o u s R eceiver/T ransm itter USART th a t is fabricated u sin g C-MOS silicon g a te technology.
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TMP82C51AP-2
/TMP82C51AP-10
TMP82C51
AM-2/TMP82C51
AM-10
P82C51A
P82C51A
82C51A
P8251A
tmp8251
P8251
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P8279
Abstract: 8279-5
Text: TOSHIBA TMP8279 PRO GRAM M ABLE KEYBOARD/DISPLAY INTERFACE TMP8279P-5 1. GENERAL DESCRIPTION T h e T M P 8 2 7 9 P -5 h e r e i n a f t e r r e f e r r e d to a s T M P 8 2 7 9 is a p r o g r a m m a b le k e y b o a rd /d isp la y in te rfa c e d e sig n e d for u se as th e T L C S -85 A m ic ro c o m p u te r p e rip h e ra l.
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TMP8279P-5
TMP8279
MPU85-314
MPU85-315
P8279
8279-5
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P8085AH
Abstract: TMP8085AP TMP8085AP-2 TMP8085 TMP8156P MPU85-9
Text: TO SHIBA TMP8085A TMP8085AP-2/TMP8085AHP-2 8-BIT MICROPROCESSOR 1. GENERAL DESCRIPTION The TMP8085AP-2/TMP8085AHP-2, hereafter on referred to as TMP8085A, is a 8 bit micro processing unit MPU . TMP8085A uses a multiplexed data bus. The address is split between the 8 bit address bus and the 8 bit data bus. The on-chip address latches of
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TMP8085A
TMP8085AP-2/TMP8085AHP-2
TMP8085AP-2/TMP8085AHP-2,
TMP8085A,
TMP8085A
TMP8155P-2/TMP8156P-2
TMP8085A.
200nSec)
TMP8085AP-2:
P8085AHP-2:
P8085AH
TMP8085AP
TMP8085AP-2
TMP8085
TMP8156P
MPU85-9
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TMP8237
Abstract: No abstract text available
Text: T O S H IB A TMP82C37A MULTIMODE DMA CONTROLLER TMP82C37AP-5/TMP82C37AM-5/TMP82C37AT-5 1. GENERAL DESCRIPTION T h e T M P 8 2 C 3 7 A P -5 /A M -5 /A T -5 h e r e in a f t e r r e f e r r e d to a s T M P 8 2 C 3 7 A is a m u ltim o d e d ire c t m e m o ry access (DM A) c o n tro lle r.
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TMP82C37AP-5/TMP82C37AM-5/TMP82C37AT-5
TMP82C37A
MPU85-271
TMP8237
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MPU85-347
Abstract: No abstract text available
Text: TOSHIBA CUC/UP . WE C • iai7 2 4 1 _ 0 Q ia0 D 1 7 ■ 1 ~ - 5 Z 'J 3 '0 3 TOSHIBA TMP82C255A/TMP82C265A CMOS PROGRAMMABLE PERIPHERAL INTERFACE TMP82C255AN-2 / TMP82C265AF-2 TMP82C255AN-10 / TMP82C265AF-10
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TMP82C255A/TMP82C265A
TMP82C255AN-2
TMP82C265AF-2
TMP82C255AN-10
TMP82C265AF-10
TMP82C255A/TMP82C265A
TMP82C55AX2.
TMP82C265A
TMP82C255A
MPU85-347
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p8255a
Abstract: P8255AH P8255 PC317
Text: TO SH IBA TMP82C55A CMOS PROGRAM M ABLE PERIPHERAL INTERFACE TMP82C55AP-2/TMP82C55AM-2 TMP82C55AP-10/TMP82C55AM-10 1. GENERAL DESCRIPTION AND FEATURES T h e T M P 8 2 C 5 5 A h e r e in a f te r r e f e r re d to as P P I is a CM OS h ig h S p eed p rogram m able in p u t/o u tp u t in terface w ith th re e 8 -b it I/O ports. 24 I/O P o rts are divided
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TMP82C55AP-2/TMP82C55AM-2
TMP82C55AP-10/TMP82C55AM-10
TMP82C55A
P82C55
VMPU-26
p8255a
P8255AH
P8255
PC317
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P82c53
Abstract: No abstract text available
Text: T O S H IB A TMP82C53 PRO GRAM M ABLE INTERVAL TIMER TMP82C53P-2 1. GENERAL DESCRIPTION The TM P82C 53P-2 h erein after referred to as TM P82C53 is a p ro g ra m m a b le counter/tim er. It is organized as 3 independent 16 bit counters, each operates w ith a
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TMP82C53P-2
TMP82C53
53P-2
P82C53)
MPU85-91
DIP24-P-600
MPU85-92
P82c53
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MPU85-9
Abstract: P82C53
Text: TOSHIBA TMP82C53 PRO GRAM M ABLE INTERVAL TIMER TMP82C53P-2 1. GENERAL DESCRIPTION T he T M P82C 53P-2 h e re in a fte r referred to as TM P82C 53 is a p ro g ra m m a b le counter/tim er. It is organized as 3 indepen dent 16 b it counters, each operates w ith a
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TMP82C53P-2
TMP82C53
53P-2
WR489
MPU85-90
MPU85-91
DIP24-P-600
MPU85-92
MPU85-9
P82C53
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P8085A
Abstract: P8085AH tmp8085
Text: TO SH IBA TMP8085A TMP8085AP/TMP8085AP-2 TMP8085AHP/TMP8085AHP-2 8-BIT MICROPROCESSOR 1. GENERAL DESCRIPTION The TM P8085AP/TM P8085AP-2/TM P8085AHP/TM P8085AHP-2, hereafter on referred to as TMP8085A, is a 8 bit micro processing unit MPU . TMP8085A uses a
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TMP8085A
TMP8085AP/TMP8085AP-2
TMP8085AHP/TMP8085AHP-2
P8085AP/TM
P8085AP-2/TM
P8085AHP/TM
P8085AHP-2,
TMP8085A,
TMP8085A
TMP8155P/TMP8156P
P8085A
P8085AH
tmp8085
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82C79
Abstract: TMP82C79 SSOP40 fifo ram 8bit TMP82C79P-2 line scan sensor SSOP40 package 16X4 MPU85-272 D-B73C
Text: T O S H IB A TMP82C79 P R O G R A M M A B LE KEYBO ARD /D ISPLAY INTERFACE TMP82C79P-2/TMP82C79M-2 1. G EN ER A L DESCRIPTION The TM P82C79P-2/M-2 hereinafter referred to as TM P82C79 is a programmable keyboard/display interface. The keyboard portion can provide a scanned interface up to
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TMP82C79
TMP82C79P-2/TMP82C79M-2
TMP82C79P-2/M-2
TMP82C79)
64-contact
MPU85-291
40PIN
DIP40-P-600
MPU85-292
82C79
TMP82C79
SSOP40
fifo ram 8bit
TMP82C79P-2
line scan sensor
SSOP40 package
16X4
MPU85-272
D-B73C
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TMP8279P-5
Abstract: TMP8279 keyboard matrix toshiba keyboard matrix 16*8 line scan sensor 16X4 n-key rollover 16x8 dual ram tmp8279p
Text: T O S H IB A TM P8279 P R O G R A M M A B L E K E Y B O A R D /D IS P L A Y INTERFACE T M P 8 2 7 9 P -5 1. GENERAL DESCRIPTION T he T M P 8279P -5 h e re in a fte r re fe rre d to as T M P 8279 is a p ro g ra m m a b le keyboard/display interface designed for use as the TLCS-85 A m icrocom puter p eriph eral.
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TMP8279
TMP8279P-5
TMP8279)
TLCS-85
64-contact
MPU85-314
MPU85-31
TMP8279P-5
TMP8279
keyboard matrix toshiba
keyboard matrix 16*8
line scan sensor
16X4
n-key rollover
16x8 dual ram
tmp8279p
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TMP82C79P-2
Abstract: 82c79 TMP82C79 fifo ram 8bit ssop40 16X4 TMP82C79M-2 toshiba signal multiplexing D-B73C
Text: T O S H IB A TMP82C79 P R O G R A M M A B LE KEYBO ARD /D ISPLAY INTERFACE TMP82C79P-2/TMP82C79M-2 1. G EN ER A L DESCRIPTION The TM P82C79P-2/M-2 hereinafter referred to as TM P82C79 is a programmable keyboard/display interface. The keyboard portion can provide a scanned interface up to
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TMP82C79
TMP82C79P-2/TMP82C79M-2
TMP82C79P-2/M-2
TMP82C79)
64-contact
MPU85-291
40PIN
DIP40-P-600
MPU85-292
TMP82C79P-2
82c79
TMP82C79
fifo ram 8bit
ssop40
16X4
TMP82C79M-2
toshiba signal multiplexing
D-B73C
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TMP82C54
Abstract: TMP82C53P-2 TMP82C54M-2 TMP82C54P-2 TGS 832 MPU85-9
Text: T O S H IB A TMP82C54 P R O G R A M M A B L E INTERVAL TIMER T M P 82C 54P -2 / T M P 8 2 C 5 4 M -2 The TM P82C54P-2 TM P82C54M -2 hereafter called the TM P82C54 is a low power, CMOS general-purpose programmable timer/counter. The TM P82C54 consists of 3 independent 16-bit counters to implement high-speed
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TMP82C54
TMP82C54P-2
TMP82C54M-2
TMP82C54)
TMP82C54
16-bit
TMP82C53P-2
TMP82C54P-2)
TMP82C53P-2
TMP82C54M-2
TGS 832
MPU85-9
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TCA 3089
Abstract: tmp82c55* toshiba westinghouse co 11 tcc TMP82C255A TMP82C255AN TMP82C255AN-2 TMP82C265A TMP82C265AF TMP82C255AN-10 TMP82C55AX2
Text: TOSHIBA TMP82C255A/TMP82C265A CMOS PROGRAMMABLE PERIPHERAL INTERFACE TM P82C 255AN -2 /TM P 82C 265A F -2 TM P 82C 255A N -10 / TM P82C 265AF-10 1. GENERAL DESCRIPTION A N D FEATURES The TMP82C255A/TMP82C265A is a CMOS high speed programmable input/output
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TMP82C255A/TMP82C265A
TMP82C255AN-2
/TMP82C265AF-2
TMP82C255AN-10/TMP82C265AF-10
TMP82C255A/TMP82C265A
TMP82C55AX2.
TMP82C265A
TMP82C255A
TCA 3089
tmp82c55* toshiba
westinghouse co 11 tcc
TMP82C255AN
TMP82C265AF
TMP82C255AN-10
TMP82C55AX2
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p8085ah
Abstract: P8085A p8085 P8085AP2 intel p8085a TMP8085 TMP8085ap
Text: TO SH IBA TMP8085A TMP8085AP-2/TMP8085AHP-2 8-BIT M ICROPROCESSOR 1. G EN ERAL DESCRIPTION The TM P8085AP-2/TM P8085AHP-2, hereafter on referred to as TM P8085A, is a 8 bit micro processing u n it MPU . TM P8085A uses a m ultiplexed d a ta bus. The address is
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TMP8085AP-2/TMP8085AHP-2
TMP8085A
P8085AP-2/TM
P8085AHP-2,
P8085A,
P8085A
P8155P-2/TM
P8156P-2
TMP8085A.
200nSec)
p8085ah
p8085
P8085AP2
intel p8085a
TMP8085
TMP8085ap
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p82c59a
Abstract: P82C59 icw1
Text: T O S H IB A TMP82C59A TOSHIBA MOS TYPE DEGITAL INTEGRATED CIRCUIT Silicon Monolithic CMOS Silicon Gate TMP82C59AP-2/TMP82C59AM-2 PRO GRAM M ABLE INTERRUPT CONTROLLER 1. GENERAL DESCRIPTION TM P82C59AP-2/AM -2 h erein a fter referred to as TM P82C59A is a program m able
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TMP82C59AP-2/TMP82C59AM-2
TMP82C59A
P82C59AP-2/AM
P82C59A)
MPU85-195
DIP28-P-600
MPU85-196
OP28-P-45Q
p82c59a
P82C59
icw1
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MPU85-207
Abstract: No abstract text available
Text: TOSHIBA TMP82C255A/TMP82C265B CMOS PRO G RAM M ABLE PERIPHERAL INTERFACE. TMP82C255AN-2 /TMP82C265BF-2 TMP82C255AN-10 /TMP82C265BF-10 1. GENERAL DESCRIPTION AND FEATURES The TMP82C255A/TMP82C265B is a CMOS high speed program m able input/output interface w ith six 8-bit I/O ports. The function, is almost equivalent to TMP82C55AX 2.
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TMP82C255A/TMP82C265B
TMP82C255AN-2
/TMP82C265BF-2
TMP82C255AN-10
/TMP82C265BF-10
TMP82C255A/TMP82C265B
TMP82C55AX
TMP82C265B
TMP82C255A
MPU85-207
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TMP82C54P2
Abstract: No abstract text available
Text: TO SH IBA TM P82C54 PRO GRAM M ABLE INTERVAL TIM ER TMP82C54P-2 /TM P82C54M -2 The TM P82C54P-2 TM P82C54M -2 hereafter called the TM P82C54 is a low power, CM OS general-purpose program m able tim er/counter. The TM P82C54 consists of 3 independent 16-bit counters to im plem ent high-speed
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TMP82C54P-2
P82C54M
P82C54
P82C54P-2
P82C54)
P82C54
16-bit
53P-2
P82C54P-2)
TMP82C54P2
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Untitled
Abstract: No abstract text available
Text: T O S H IB A 1. TMP68303 INTRODUCTION This product is an ASSP Application Specific Standard product w ith a 68HC000 MPU core and built-in serial I/F, p arallel I/F, tim er, in te rru p t controller, address decoder, DMA controller, DRAM controller and stepping motor controller as peripheral
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TMP68303
68HC000
16MHz
32-bit
10-bit
12-channel
MPU-200
TMP68303.
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TMP82C265BF-10
Abstract: TMP82C255A TMP82C255AN-10 TMP82C255AN-2 tmp82c265bf tmp82c55* toshiba MPU85 TMP82C265BF-2
Text: T O S H IB A TMP82C255A/TMP82C265B CMOS PROGRAMMABLE PERIPHERAL INTERFACE T - 5 2 .- 3 3 - S 3 TMP82C255AN-2 /TMP82C265BF-2 TMP82C255AN-10 /TMP82C265BF-10 1. GENERAL DESCRIPTION AND FEATURES The TMP82C255A/TMP82C265B is a CMOS high speed programmable input/output
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TMP82C255A/TMP82C265B
-33-SZ
TMP82C255AN-2
/TMP82C265BF-2
TMP82C255AN-10
/TMP82C265BF-10
TMP82C255A/TMP82C265B
TMP82C55AX2.
TMP82C265B
TMP82C255A
TMP82C265BF-10
tmp82c265bf
tmp82c55* toshiba
MPU85
TMP82C265BF-2
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8156p
Abstract: tmp8155p p8155 TMP8155 TMP8155P-2 TMP8156P-2
Text: T O S H IB A TM P8155/8156 TMP8155P-2/TMP81 56P-2 256 BYTE STATIC RAM W ITH I/O PORTS AN D TIM ER 1. G EN ERA L DESCRIPTION The TM P8155/8156P-2 are RAM including I/O ports an d counter/tim er on one chip for usin g in th e TLCS-85A m icrocom puter system . T he RAM portion is designed w ith 2K
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TMP81
TMP8155P-2/TMP81
56P-2
TMP8155/8156P-2
TLCS-85A
MPU85-40
TMP8155/8156
40Pins
DIP40-P-600
MPU85-41
8156p
tmp8155p
p8155
TMP8155
TMP8155P-2
TMP8156P-2
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TMP8251A PROGRAMM ABLE COMMUNICATION INTERFACE TM P8251AP 1. GENERAL DESCRIPTION The TMP8251AP is the industry standard Universal Synchronous/Asynchoronous Receiver/Transmitter USART that is fabricated using N-channel silicon gate MOS technology.
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TMP8251A
P8251AP
TMP8251AP
TMP8251A
28pin
MPU85-77
DIP28-P-600
99TYP
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Untitled
Abstract: No abstract text available
Text: T O S H IB A TMP82C59A TOSHIBA MOS TYPE DEGITAL INTEGRATED CIRCUIT Silicon Monolithic CMOS Silicon Gate TMP82C59AP-2/TMP82C59AM-2 PROGRAM M ABLE INTERRUPT CONTROLLER 1. GENERAL DESCRIPTION T M P 82C 59A P -2/A M -2 h ere in after referred to a s T M P 8 2 C 5 9 A is a p ro gram m ab le
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TMP82C59A
TMP82C59AP-2/TMP82C59AM-2
MPU85-195
DIP28-P-600
MPU85-196
50P28-P-450
MPU85-197
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A-PC06
Abstract: TMP82C255A TMP82C255AN-10 TMP82C255AN-2 TMP82C265A TMP82C265AF-10 MPU85
Text: TO SH IB A TMP82C255A/TMP82C265A CM OS PR O G R A M M A B LE PERIPH ER A L INTERFACE TMP82C255AN-2 /TMP82C265AF-2 TMP82C255AN-10 / TMP82C265AF-10 1. G EN ER A L DESCRIPTION AN D FEATURES The TMP82C255A/TMP82C265A is a CMOS high speed programmable input/output
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TMP82C255A/TMP82C265A
TMP82C255AN-2
/TMP82C265AF-2
TMP82C255AN-10
TMP82C265AF-10
TMP82C255A/TMP82C265A
TMP82C55AX2.
TMP82C265A
TMP82C255A
A-PC06
TMP82C265AF-10
MPU85
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