Untitled
Abstract: No abstract text available
Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
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Delta39Kâ
64-bit
39K200-208EQFP
39K165
39K200
-233MHz
Delta39K165Z
144-FBGA
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PDF
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84 FBGA
Abstract: 39K100 39K200 39K30 39K50 388-BGA
Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs
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Original
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Delta39KTM
66-MHz
64-bit
39K165
208-EQFP,
484-FBGA,
388-BGA,
676-FBGA
84 FBGA
39K100
39K200
39K30
39K50
388-BGA
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PDF
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8kx1 RAM
Abstract: No abstract text available
Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs
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Original
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Delta39KTM
233-MHz
MIL-STD-883"
/JESD22A114-A
39K50
39K30
Delta39K
39K165/200
CY3LV002
CY3LV020.
8kx1 RAM
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PDF
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39k200
Abstract: CY39200V
Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs
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Original
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Delta39KTM
250-MHz
39k200
CY39200V
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PDF
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CY39100V484B-125BBI
Abstract: programmable slew rate control IO AT17LV010-10JI CY39030V256-125MBC IO1 5V 39K100 39K165 39K30 39K50 CY39100V208B-125NTC
Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
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Original
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Delta39KTM
66-MHz
64-bit
39K165
MG388
CY39030
-256FBGA
CY39100V484B-125BBI
programmable slew rate control IO
AT17LV010-10JI
CY39030V256-125MBC
IO1 5V
39K100
39K30
39K50
CY39100V208B-125NTC
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PDF
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39K100
Abstract: 39K30 39K50
Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features — Clock polarity control at each register • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2
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Original
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Delta39KTM
64-bit
39K200-208EQFP
39K165
39K200
-233MHz
Delta39K165Z
39K100
39K30
39K50
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PDF
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CY39200V
Abstract: No abstract text available
Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin
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Original
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Delta39KTM
NT208
51-85069-B
388-Lead
MG388
256-Ball
BB256/MB256
1-85108-A
CY39200V
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PDF
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delta39k
Abstract: 39K100 39K30 39K50
Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
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Original
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Delta39KTM
64-bit
39K165
MG388
CY39030
-256FBGA
delta39k
39K100
39K30
39K50
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PDF
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delta39k
Abstract: 39K100 39K165 39K30 39K50 CY3LV010 CY39200V
Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs
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Original
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Delta39KTM
64-bit
Delta39K
39K165/200
CY3LV002
CY3LV020.
Delta39K.
39K100
39K165
39K30
39K50
CY3LV010
CY39200V
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PDF
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bga 484 0.8mm pitch
Abstract: 20532 tqfp 39K100 39K200 39K30 39K50 484FBGA CY39200V208-181NTXC CY39100V208B-125NTxC cy39030v208-125ntxc
Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs
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Original
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Delta39KTM
66-MHz
64-bit
39K165
208-EQFP,
484-FBGA,
388-BGA,
676-FBGA
bga 484 0.8mm pitch
20532 tqfp
39K100
39K200
39K30
39K50
484FBGA
CY39200V208-181NTXC
CY39100V208B-125NTxC
cy39030v208-125ntxc
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PDF
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CY39100V484-125BBI
Abstract: "Single-Port RAM" delta39k
Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin
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Original
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Delta39KTM
CY39100V484-125BBI
"Single-Port RAM"
delta39k
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PDF
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NT208
Abstract: 1kx8 rom 250NTC
Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Carry-chain logic for fast and efficient arithmetic operations •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
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Original
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Delta39KTM
250-MHz
NT208
1kx8 rom
250NTC
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PDF
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