EP2C20
Abstract: DDR2 pin out EP2C15A F256 EP2C20A
Text: Cyclone II EP2C15A, EP2C20 & EP2C20A Device Pin-Out PT-EP2C20-2.1 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are
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EP2C15A,
EP2C20
EP2C20A
PT-EP2C20-2
x16/x18
EP2C15A
EP2C20
DDR2 pin out
F256
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EP2C20
Abstract: EP2C15A F256 LVDS48
Text: Pin Information for the Cyclone II EP2C15A, EP2C20 & EP2C20A Devices Version 1.8 Note 1 , (2) Bank Number VREFB Group Pin Name / Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0
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EP2C15A,
EP2C20
EP2C20A
x16/x18
EP2C15A
EP2C20
F256
LVDS48
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lvds125
Abstract: F324 F400
Text: Pin Information for the Cyclone EP1C4 Device Version 1.3 Bank Number VREFB Group Pin Name / Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF0B1 VREF0B1 VREF0B1
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dl179
Abstract: LVD179 SN65LVDS050 SN65LVDS051 SN65LVDS179 SN65LVDS179D SN65LVDS179DGK SN65LVDS180 LVDS79 SLLS301G
Text: SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS301G – APRIL 1998 – REVISED MARCH 2000 D D D D D D D D D D D Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard Signaling Rates up to 400 Mbit/s
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SN65LVDS179,
SN65LVDS180,
SN65LVDS050,
SN65LVDS051
SLLS301G
TIA/EIA-644-1995
dl179
LVD179
SN65LVDS050
SN65LVDS051
SN65LVDS179
SN65LVDS179D
SN65LVDS179DGK
SN65LVDS180
LVDS79
SLLS301G
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ep2c20
Abstract: EP2C15A F256
Text: Pin Information for the Cyclone II EP2C15A, EP2C20 & EP2C20A Devices Version 2.0 Notes 1 , (2) Bank Number VREFB Group Pin Name / Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0
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EP2C15A,
EP2C20
EP2C20A
x16/x18
EP2C15A
ep2c20
F256
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EP1C12
Abstract: F256 F324
Text: Pin Information for the Cyclone EP1C12 Device Final version 1.2 Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF Bank VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1
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EP1C12
LVDS23p
LVDS23n
LVDS22p
LVDS22n
LVDS21p
LVDS21n
F256
F324
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EP1C12 pin diagram
Abstract: F324 LVDS73P EP1C12 F256 PT-EP1C12-1 LVDS92p LVDS86
Text: Pin Information for the Cyclone EP1C12 Device Version 1.4 Bank Number VREF Bank Pin Name/Function Optional Function s Configuration Function Q240 F256 F324 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1
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EP1C12
LVDS23p
LVDS23n
LVDS22p
LVDS22n
PT-EP1C12-1
EP1C12 pin diagram
F324
LVDS73P
F256
LVDS92p
LVDS86
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EP2C35
Abstract: LVDS93 LVDS179
Text: Cyclone II EP2C35 Device Pin-Out PT-EP2C35-1.9 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
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EP2C35
PT-EP2C35-1
LVDS93
LVDS179
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mark 3t1
Abstract: EP2C50 LVDS54P LVDS93
Text: Cyclone II EP2C50 Device Pin-Out PT-EP2C50-1.6 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
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EP2C50
PT-EP2C50-1
mark 3t1
LVDS54P
LVDS93
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mark 3t1
Abstract: lvds228 PT-EP2C70-1 Cyclone II EP2C70
Text: Cyclone II EP2C70 Device Pin-Out PT-EP2C70-1.7 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
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EP2C70
PT-EP2C70-1
mark 3t1
lvds228
Cyclone II EP2C70
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Untitled
Abstract: No abstract text available
Text: SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS301I – APRIL 1998 – REVISED DECEMBER 2000 D D D D D D D D D D D Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard Signaling Rates up to 400 Mbit/s
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SN65LVDS179,
SN65LVDS180,
SN65LVDS050,
SN65LVDS051
SLLS301I
TIA/EIA-644-1995
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LM1117-1.2
Abstract: BOX Header 2X20M EP2S35 7segment 2X20M BC59 IOB33 EP2C20 MAX232 G4 m3128
Text: 5 4 3 2 1 Altera Cyclone II FPGA Starter Board D SCHEMATIC TOP AUDIO DISPLAY EP2C20 INPUT MEMORY POWER BLASTER CONTENT PAGE COVER PAGE , TOP WM8731 VGA , 7SEGMENT ,LED EP2C20 BANK1.BANK8 , POWER , CONFIG CLOCK , PS2 , RS232 , KEY , SWITCH , CONNECT SRAM , DRAM , FLASH , SD CARD
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EP2C20
WM8731
EP2C20
RS232
24MHZ
LM1117-1.2
BOX Header 2X20M
EP2S35
7segment
2X20M
BC59
IOB33
MAX232 G4
m3128
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BGA and QFP Altera Package mounting
Abstract: diode zener ph c5v1 527 MOSFET TRANSISTOR motorola PH C5V1 lt1085 linear SOIC Package 8-Pin Surface Mount 601 "Fast Cycle RAM" mounting pad dimentions PQFP motorola smd transistor code 621 BGA OUTLINE DRAWING
Text: Cyclone Device Handbook, Volume 1 Preliminary Information 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com C5V1-1.0 Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
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00-mm
BGA and QFP Altera Package mounting
diode zener ph c5v1
527 MOSFET TRANSISTOR motorola
PH C5V1
lt1085 linear
SOIC Package 8-Pin Surface Mount 601
"Fast Cycle RAM"
mounting pad dimentions PQFP
motorola smd transistor code 621
BGA OUTLINE DRAWING
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SB5B5
Abstract: EP2C50
Text: Pin Information for the Cyclone II EP2C50 Device Version 1.5 Note 1 , (2) Bank Number VREFB Group Pin Name / Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0
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EP2C50
SB5B5
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F896
Abstract: T25 4 J6 lvds228 EP2C70
Text: Pin Information for the Cyclone II EP2C70 Device Version 1.6 Note 1 , (2) Bank Number VREFB Group Pin Name / Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0
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EP2C70
F896
T25 4 J6
lvds228
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Untitled
Abstract: No abstract text available
Text: SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS301I – APRIL 1998 – REVISED DECEMBER 2000 D D D D D D D D D D D Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard Signaling Rates up to 400 Mbit/s
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SN65LVDS179,
SN65LVDS180,
SN65LVDS050,
SN65LVDS051
SLLS301I
TIA/EIA-644-1995
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F324
Abstract: F400
Text: Pin Information for the Cyclone EP1C20 Device Final version 1.1 Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF Bank VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1
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EP1C20
LVDS31p
LVDS31n
LVDS30p
LVDS30n
F324
F400
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