53413
Abstract: 58725 632367 594971
Text: Altera Digital Library CD-ROM December 2002 CD-ADL2002-4.0 Legal Notice This CD ROM contains documentation and other information related to products and services of Altera Corporation “Altera” which is provided as a courtesy to Altera’s customers and potential customers. By copying or using any information contained on this CD ROM, you agree to be bound by the
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Original
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CD-ADL2002-4
Incorpora6596;
RE37060;
RE35977;
53413
58725
632367
594971
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truth table for ic 74138
Abstract: 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
Text: PLCAD-SUPREME & PLS-SUPREME A+PLUS Programmable Logic Development System & Software Data Sheet September 1991, ver. 1 Features J J J J □ □ H igh-level su p p o rt for A ltera's general-purpose Classic EPLDs M ultiple design entry m ethods LogiCaps schem atic capture
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44-Mbyte,
386-based
truth table for ic 74138
16CUDSLR
ALU IC 74183
IC 74151 diagram and truth table
74183 alu
74147 pin diagram and truth table
pin diagram of IC 74184
HP-7475A
7408 ic truth table
IC 74373 truth table
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D5032
Abstract: IC TTL 7400 free J1810 Altera LP5 PLDS-ENCORE plej5128
Text: PLDS-ENCORE MAX+PLUS, A+PLUS & SAM+PLUS Programmable Logic Development System Data Sheet September 1991, ver. 2 Contents □ □ □ □ □ General Description P L S -M A X — M A X + P L U S P ro g ra m m ab le Logic Softw are P L S - S U P R E M E — A + P L U S P ro g ra m m a b le L ogic Softw are
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J1810
J5064
PLED910
486-based
D5032
IC TTL 7400 free
Altera LP5
PLDS-ENCORE
plej5128
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PDF
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EPLD 5128
Abstract: No abstract text available
Text: September 1991, ver. 2 Introduction Application Brief 73 Altera provides a variety of softw are utility pro gra m s that co m p le m e n t the M A X + P L U S II, M A X + P L U S , A + P L U S , S A M + P L U S , a n d M C M a p d ev elop m en t systems. These pro gram s are available via Altera's electronic bulletin board service
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800-EPLD
11-compatible
EPLD 5128
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schematic diagram cga to vga
Abstract: TTL 7400 TTL 7400 full
Text: PLS2 V A A+PLUS PROGRAMMABLE LOGIC USER SOFTWARE DI Q O I L Ù L FEATURES GENERAL DESCRIPTION • Software support for all Altera General-Purpose EP-Series EPLDs. A+PLUS, Altera Programmable logic user software, contained in the PLS2 product, is a series of software
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TTL 74139
Abstract: 74153 mux MSI 74148 16cudslr CI 74138 sn 74373 8mcomp 7404 7408 7432 7408, 7404, 7486, 7432 Flip-Flop 7471
Text: PLSLIB-TTL /$ ^ n^ X LIBRARY • TTL MacroFunction Library Diskette. • ADLIB, Altera Design Librarian Diskette. To increase design ease and productivity Altera has created M acroFunctions. These are high level building blocks that allow the user to design at
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shiftregisters
Abstract: EP910 altera TTL library 74LS series logic gates 74LS EP1810 EP1810-45 EP610 PLE40 altera logicaps TTL library
Text: EP1810 Y 7 \ m HIGH PERFORMANCE 4 8 MACROCELL EPLD m 10 I U FEATURES GENERAL DESCRIPTION • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conven tional and custom logic. • Speed equivalent to 74LS TTL with 33 MHz clock
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Altera EP1800
Abstract: EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
Text: EP1800 Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conventional and custom logic. Speed equivalent to 74LS TTL with 25 MHz clock rates. “Zero Power” typically 10/jA standby . Active power of 250 mW at 5 MHz.
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EP1800
Altera EP1800
EP1800 JEDEC FORMAT
EP1800
altera logicaps TTL library
SCHEMA PA BUILT UP
EP1800 LOGIC DIAGRAM
ep18001
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ALTERA EP1810LC-45
Abstract: EP1810LC-45 EP1810LC-35 EP1810JC-45 EP1810jC-35 EP1810JC EP1810LC45
Text: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3232. FEBRUARY 1989-R E V IS E D AUGUST 1989 • Erasable, User-Configurable LSI Circuit Capable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic CHIP-CARRIER PACKAGE
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EP1810
48-MACROCELL
D3232.
1989-R
33-MHz
ALTERA EP1810LC-45
EP1810LC-45
EP1810LC-35
EP1810JC-45
EP1810jC-35
EP1810JC
EP1810LC45
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full adder using ic 74138
Abstract: full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 Application of Multiplexer IC 74151 IC 74138 74138 IC decoder Multiplexer IC 74151
Text: EP1800JC-EV1 EP1800JC-EV1 EVALUATION CHIP • Advanced CHMOS circuitry features low power, high performance, and high noise immunity power consumption, high noise margins, and ease of design. The EP1800 is implemented in a sub 2-micron dual-polysilicon CHMOS floating gate EPROM tech
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EP1800JC-EV1
EPt800
68-pin
EP1800JC-EV1
0UT20
0UT21
OUT22
0UT23
full adder using ic 74138
full adder using Multiplexer IC 74151
decoder IC 74138
TTL 74194
74151 multiplexer
pin configuration of IC 74138
Application of Multiplexer IC 74151
IC 74138
74138 IC decoder
Multiplexer IC 74151
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9852
Abstract: schematic diagram vga schematic diagram cga to vga
Text: PLE40 \ LOGIC APS SCHEMATIC CAPTURE SOFTWARE PLE40 CONTENTS GENERAL DESCRIPTION SOFTWARE Digital logic designs are often o rigin ally con ceived in the form of a logic or schematic diagram. The engineer wishing to take advantage of the many benefits of the new high density program
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74194 shift register
Abstract: 74377 register logicaps shift register by using D flip-flop 7474 74191 counter 74377 Latches 74373 altera logicaps TTL library 74374 74373 ttl 74191
Text: €Pßl400 PROGRAMMABLE BUS PERIPHERAL FEATURES GENERAL DESCRIPTION • Bus I/O —Register Intensive Buster EPLD The EPB1400 (Buster) EPLD from Altera repre sents the firs t M icro proce ssor Peripheral UserConfigurable at the Silicon level. The device consists
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25MHz
EPB1400
EPB1400
74194 shift register
74377 register
logicaps
shift register by using D flip-flop 7474
74191 counter
74377
Latches 74373
altera logicaps TTL library
74374 74373
ttl 74191
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IC 74373
Abstract: IC 74373 truth table logitech 99 mouse IC function of latch ic 74373
Text: USER-CONFIGURABLE r Q Q 1 /1 0 0 MICROPROCESSOR PERIPHERAL E r D I ^ H J U \ GENERAL DESCRIPTION FEATURES Bus I/O — Register Intensive B U S T ER EPLD. Erasable, User-Configurable Logic Device for Customized Microprocessor Peripheral Functions. Byte-Wide Microprocessor Bus Port with
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32-bit
25MHz
Dri22
EPB1400
IC 74373
IC 74373 truth table
logitech 99 mouse IC
function of latch ic 74373
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EPS448
Abstract: Altera EP1800 altera ep320
Text: Surface-Mount EPLDs 20 to 28-Lead Package Supplement Data Sheet March 1990 This supplement provides the specifications for Altera's 20-, 24-, and 28-pin plastic surface-mount packaging options. The specifications consist of physical dimensions and thermal characteristics for plastic Small Outline
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28-Lead
28-pin
EP330,
EP630,
EPM5016,
EPM5024,
EPM5032
300-m
EP330
20-pin
EPS448
Altera EP1800
altera ep320
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Altera LP5
Abstract: Altera EP1800 logicaps schematic capture EPM5016 EP1810 PLEj1810 PLDS-MAX ep330 EPS448D 02D-00209
Text: AN Ü □ !^ V a \ Product Selection Guide Data Sheet September 1991, ver. 2 In t r o d u c t io n P r°d u c t Selection G uid e summarizes the range of products available from Altera: U □ U Ü U U U General-purpose E P L D s Function-specific E P L D s
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PLEG5192
PLED448
PLEJ448
PLEJ464
PLMJ464
PLEQ464
PLEJ2001
P600/610/610A/610T/630
P900/910/910A/910T
800/1810/1810T/1830
Altera LP5
Altera EP1800
logicaps schematic capture
EPM5016
EP1810
PLEj1810
PLDS-MAX
ep330
EPS448D
02D-00209
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PDF
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EP1200
Abstract: Altera ep1200
Text: ry T \ u s e r -c o n fig u r a b le MICROPROCESSOR PERIPHERAL C D D U n n C i D I t U U GENERAL DESCRIPTION FEATURES Bus I/O — Register Intensive BUSTER EPLD. Erasable, User-Configurable Logic Device for Customized Microprocessor Peripheral Functions.
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32-bit
25MHz
EPB1400
EP1200
Altera ep1200
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PL-ASAP
Abstract: altera EP300 Altera EP1800 EP1200 ple3-12a altera LP4 Altera ep1200 ep320 EPS448 EPMS130
Text: Datasheet EPB2001 and the Micro Channel Bus MC Bus . The EPB2001 is an ideal chip for manufacturers of IBM PS/2 add-on cards based on Micro Channel Architecture (MCA) since it allows programming of specific card characteristics for a specific application. The EPB2001's integrated functions
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EPB2001
C0M90C84
PL-ASAP
altera EP300
Altera EP1800
EP1200
ple3-12a
altera LP4
Altera ep1200
ep320
EPS448
EPMS130
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EPB2001LC
Abstract: altera ep320 altera EP300 EP600 programming program altera ep320 COM90C84 PLDS-MCMAP EPM5127 altera LP4 PLEJ2001
Text: EPB2001 D atasheet and the Micro Channel Bus MC Bus . The EPB2001 is an ideal chip for manufacturers of IBM P S /2 add-on cards based on Micro Channel Architecture (MCA) since it allows programming of specific card characteristics for a specific application. The EPB2001's integrated functions
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EPB2001
EPB2001LC
altera ep320
altera EP300
EP600 programming
program altera ep320
COM90C84
PLDS-MCMAP
EPM5127
altera LP4
PLEJ2001
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PDF
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EP1810JC-35
Abstract: programming manual EP910 EP1810LC-35 OLC-45 EP1810JC35 programming manual EPLD EP1810LI-45 EP1810JC EP1810I Erasable Programmable Logic Device
Text: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3232. FEBHUARY 1989-REVISED AUGUST 1989 CHIP-CARRIER PACKAGE Erasable, U ser-Configurable LSI Circuit C apable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic
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EP1810
48-MACROCELL
D3232.
1989-REVISED
33-MHz
68-pin
28Cll
EP1810JC-35
programming manual EP910
EP1810LC-35
OLC-45
EP1810JC35
programming manual EPLD
EP1810LI-45
EP1810JC
EP1810I
Erasable Programmable Logic Device
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7400 databook
Abstract: 7400 TTL logitech TTL LS 7400
Text: TTL schematic designs processed and imple mented in EPLDs by Altera. Two programmed EPLDs returned to you. PLSTART coupon good for processing two designs. Runs on IBM XT, AT and compatible personal computers. Graphical entry of logic schematics: — Design schematics using TTL MacroFunctions
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74245 BUFFER IC
Abstract: pin diagram of 74245 BUFFER IC IC 74245 latch 74373 80386 microprocessor pin out diagram 74245 buffer 74373 cmos dual s-r latch 74245 BIDIRECTIONAL BUFFER data 74245 20 pin ic Ob2 tube
Text: V 7 \ USER-CONFIGURABLE m ic r o p r o c e s s o r p e r ip h e r a l C D D 1/100 L rD I4 U U FEATURES GENERAL DESCRIPTION • Bus I/O — Register Intensive BUSTER EPLD. • Erasable, User-Configurable Logic Device for Customized Microprocessor Peripheral
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32-bit
25MHz
EPB1400-2
EPB1400
100pF.
74245 BUFFER IC
pin diagram of 74245 BUFFER IC
IC 74245
latch 74373
80386 microprocessor pin out diagram
74245 buffer
74373 cmos dual s-r latch
74245 BIDIRECTIONAL BUFFER data
74245 20 pin ic
Ob2 tube
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PDF
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EP1810JC-45
Abstract: logicaps schematic capture manual programming manual EP910 Flip flop JK cmos
Text: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLO D3232, FEB RU ARY 1 9 8 9 -R E V IS E D AU GU ST 1989 • Erasable, User-Configurable LSI Circuit Capable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic
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EP1810
48-MACROCELL
D3232,
33-MHz
EP1810JC-45
logicaps schematic capture manual
programming manual EP910
Flip flop JK cmos
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PDF
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PLS-SAM
Abstract: logicaps schematic capture PLED448 PLS-MAX PLEJ5128
Text: g _ n V A \ 1 1— /— vA PR O G RA M M ABLE LOGIC DEVELOPM ENT SYSTEM -ENCO RE n i H O r ilH A n f P L D S ^ N IÜ H E PLDS-ENCORE CONTENTS GENERAL DESCRIPTION • • • • • • • PLDS-ENCORE is the most comprehensive EPLD development software package available. It sup
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PLED5032
PLEJ5128
PLED448
PLED1400
12-Month
PLS-SAM
logicaps schematic capture
PLS-MAX
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