TI BINARY DATE CODE
Abstract: BQ20Z80-V101 BQ2940
Text: bq20z80-V101 www.ti.com SLUS625C – SEPTEMBER 2004 – REVISED JULY 2005 SBS 1.1-COMPLIANT GAS GAUGE ENABLED WITH IMPEDANCE TRACK TECHNOLOGY FOR USE WITH THE bq29312 FEATURES • • • • • • • • • • • • • • • Patented Impedance Track™ Technology
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bq20z80-V101
SLUS625C
bq29312
TI BINARY DATE CODE
BQ2940
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Untitled
Abstract: No abstract text available
Text: iPEM 2.4 Gb SDRAM-DDR2 AS4DDR232M72PBG 32Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES BENEFITS DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: • 255 Plastic Ball Grid Array PBGA , 25 x 32mm
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AS4DDR232M72PBG
32Mx72
AS4DDR232M72PBG
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TAG 8926
Abstract: Lpg 899 SDC 2921 TF 6221 HEN LED display 12V+RELAY+1+C/8 pin ic sdc 3733
Text: MCIMX31 and MCIMX31L Multimedia Applications Processors Reference Manual MCIMX31RM Rev. 1 2/2006 How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130
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MCIMX31
MCIMX31L
MCIMX31RM
IOIS16
IOIS16/WP
MCIMX31L
TAG 8926
Lpg 899
SDC 2921
TF 6221 HEN LED display
12V+RELAY+1+C/8 pin ic sdc 3733
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unseal BQ2084
Abstract: unseal BQ20z80 103AT bq20z80 bq20z80DBT bq20z80DBTR bq29312 bq29400 VIT140 0x2673
Text: bq20z80 www.ti.com SLUS625B – SEPTEMBER 2004 – REVISED DECEMBER 2004 SBS 1.1-COMPLIANT GAS GAUGE ENABLED WITH ImpedanceTrack TECHNOLOGY FOR USE WITH THE bq29312 FEATURES • • • • • • • • • • • • • • Patented ImpedanceTrack Technology
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bq20z80
SLUS625B
bq29312
unseal BQ2084
unseal BQ20z80
103AT
bq20z80DBT
bq20z80DBTR
bq29400
VIT140
0x2673
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PDF
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TMS320DM357
Abstract: No abstract text available
Text: TMS320DM357 DVEVM v2.05 Getting Started Guide Literature Number: SPRUGH0 December 2008 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any
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TMS320DM357
511458-0001B
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Untitled
Abstract: No abstract text available
Text: TMS320F28377D, TMS320F28376D www.ti.com SPRS880 – DECEMBER 2013 TMS320F2837xD Dual-Core Delfino Microcontrollers Check for Samples: TMS320F28377D, TMS320F28376D 1 TMS320F2837xD Dual-Core Delfino MCUs 1.1 Features • Dual-Core Architecture – Two TMS320C28x™ 32-Bit CPUs
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TMS320F28377D,
TMS320F28376D
SPRS880
TMS320F2837xD
TMS320C28xâ
32-Bit
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AF200 microcontroller programmer
Abstract: SKwizard AF200 fujitsu STARTERkit mb90f MB90F520 minato 1890A J6 marking code MB90523 MB90570 QFP120
Text: QFP120 Flash-Test-Board Documentation Fujitsu Mikroelektronik GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag, Germany Revision: Date: 3.0 20/07/1998 Documentation Flash Test Board Contents Hardware description of QFP120 Flash-Test-Board _ 3
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QFP120
i19200
-SK16
-i19200
-i19200
-FF0000
FFA000
AF200 microcontroller programmer
SKwizard
AF200
fujitsu STARTERkit mb90f
MB90F520
minato 1890A
J6 marking code
MB90523
MB90570
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Untitled
Abstract: No abstract text available
Text: M24LR16E-R Dynamic NFC/RFID tag IC with 16-Kbit EEPROM, energy harvesting, I²C bus and ISO 15693 RF interface Datasheet - production data Contactless interface • ISO 15693 and ISO 18000-3 mode 1 compatible • 13.56 MHz ±7k Hz carrier frequency SO8 MN
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M24LR16E-R
16-Kbit
64-bit
32-bity
DocID018932
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Untitled
Abstract: No abstract text available
Text: LRI2K 2048 bit EEPROM TAG IC at 13.56 MHz with 64-bit UID and KILL code, ISO15693 and ISO18000-3 Mode 1 compliant Preliminary Data Features • ISO15693 standard fully compliant ■ ISO18000-3 mode 1 standard fully compliant ■ 13.56 MHz ±7k Hz carrier frequency
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64-bit
ISO15693
ISO18000-3
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Untitled
Abstract: No abstract text available
Text: SRI512 13.56-MHz short-range Contactless memory chip with 512-bit EEPROM and Anti-Collision functions Preliminary Data Feature summary • ISO 14443 - 2 Type B Air Interface Compliant ■ ISO 14443 - 3 Type B Frame Format Compliant ■ 13.56MHz Carrier Frequency
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SRI512
56-MHz
512-bit
56MHz
847kHz
64-bit
40-Year
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PDF
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PC133 registered reference design
Abstract: MT48LC32M8A2P
Text: 256MB / 512MB x64 168-PIN SDRAM DIMMs SYNCHRONOUS DRAM MODULE MT8LSDT3264A(I) - 256MB MT16LSDT6464A(I) - 512MB For the latest data sheet, please refer to the Micron Web site: www.micron.com/moduleds Features Figure 1: 168-Pin DIMM (MO–161) • PC100- and PC133-compliant
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256MB
512MB
168-PIN
PC100-
PC133-compliant
168-pin,
256MB
MT8LSDT3264A
64x64AG
PC133 registered reference design
MT48LC32M8A2P
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Untitled
Abstract: No abstract text available
Text: White Electronic Designs W3DG64126V-D2 PRELIMINARY* 1GB - 2x64Mx64, SDRAM UNBUFFERED FEATURES DESCRIPTION PC100 and PC133 compatible The W3DG64126V is a 2x64Mx64 synchronous DRAM module which consists of sixteen 64Mx8 SDRAM components in TSOP II package and one 2K EEPROM
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W3DG64126V-D2
2x64Mx64,
PC100
PC133
W3DG64126V
2x64Mx64
64Mx8
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MT48v32m16
Abstract: No abstract text available
Text: PRELIMINARY‡ 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM SYNCHRONOUS DRAM MT48LC32M16S2 MT48LC16M16T2 MT48LC16M16B2 Features • • • • • • • • • • • • • MT48V16M16B2 MT48H32M16S2 MT48H16M16T2 MT48H16M16B2 1 2 3 A VSS DQ15 B DQ14 C 4
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256Mb
512Mb:
192-cycle
MT48LC32M16S2
MT48LC16M16T2
MT48LC16M16B2
MT48V32M16S2
MT48H32M16S2
MT48V16M16T2
MT48H1a
MT48v32m16
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ISO10373-6
Abstract: SRT512 ISO14443-2 MI b11 transistor A4t 46 diode a4t transistor A4t ISO14443 ISO14443-3 7816-6 AM1
Text: SRT512 13.56 MHz short-range Contactless memory chip with 512-bit EEPROM and anticollision functions Features • ISO 14443-2 Type B Air Interface compliant ■ ISO 14443-3 Type B Frame Format compliant ■ 13.56 MHz carrier frequency ■ 847 kHz subcarrier frequency
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SRT512
512-bit
64-bit
40-year
ISO10373-6
SRT512
ISO14443-2
MI b11
transistor A4t 46
diode a4t
transistor A4t
ISO14443
ISO14443-3
7816-6 AM1
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Untitled
Abstract: No abstract text available
Text: 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178A − DECEMBER 1991 − REVISED FEBRUARY 1998 D Inputs Are TTL-Voltage Compatible D Asynchronous Clear D Fully Independent Clock Circuit Simplifies D D D D DW PACKAGE TOP VIEW
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74ACT11867
SCAS178A
500-mA
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R5F56218
Abstract: R5F56216 DTC142EE R5F562N8 R0E000010KCE00 R5F562T7 R5F562T6 R5F562TA E1 Emulator R0E000010KCE00 RX62T
Text: User’s Manual E1/E20 Emulator Additional Document for User’s Manual Notes on Connection Supported Devices: RX Family / RX600 Series RX610, RX621, RX62N and RX62T Groups NOTICE: There is a correction in "Figure 2.15 Interface Circuit in the E20 Emulator (1)"
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E1/E20
RX600
RX610,
RX621,
RX62N
RX62T
20Emulator
R20UT0399EJ0300
REJ10J2090-0200)
R5F56218
R5F56216
DTC142EE
R5F562N8
R0E000010KCE00
R5F562T7
R5F562T6
R5F562TA
E1 Emulator R0E000010KCE00
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VC5471
Abstract: No abstract text available
Text: TMS320VC5471 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS180C June 2001 – Revised December 2002 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments
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TMS320VC5471
SPRS180C
VC5471
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soc fuse
Abstract: SLUS681
Text: bq20z80-V102 www.ti.com SLUS681 – NOVEMBER 2005 SBS 1.1-COMPLIANT GAS GAUGE ENABLED WITH IMPEDANCE TRACK TECHNOLOGY FOR USE WITH THE bq29312A FEATURES • • • • • • • • • • • • • • • Patented Impedance Track™ Technology Accurately Measures Available Charge in
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bq20z80-V102
SLUS681
bq29312A
soc fuse
SLUS681
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AT697
Abstract: AT697F AT697E 4426D ASR16
Text: Features • SPARC V8 High Performance Low-power 32-bit Architecture • • • • • • • • • • • • • • – LEON2-FT 1.0.13 compliant – 8 Register Windows Advanced Architecture: – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data Cache
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32-bit
24-bit
33MHz
32/64-bit
4426D
AT697
AT697F
AT697E
ASR16
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MB87P2020
Abstract: MB87J2120 MB91360 SAA7111
Text: Cremson Graphic Controller Family Modular Starterkit User’s Manual for board configuration MB91F361/2 CPU-Module + MB87J2120 ‘Lavender’ or MB87P2020 ‘Jasmine’ Fujitsu Microelectronics Europe GmbH Vers. 1.0 page -1- Warrenty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH
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MB91F361/2
MB87J2120
MB87P2020
SAA7111
MB87P2020
MB87J2120
MB91360
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W3DG6463V-D2
Abstract: No abstract text available
Text: White Electronic Designs W3DG6463V-D2 PRELIMINARY* 512MB – 2x32Mx64 SDRAM UNBUFFERED FEATURES DESCRIPTION Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive
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W3DG6463V-D2
512MB
2x32Mx64
W3DG6463V
32Mx8
W3DG6463V-D2
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Untitled
Abstract: No abstract text available
Text: SRIX4K 13.56MHz Short Range Contactless Memory Chip with 4096 bit EEPROM, Anti-Collision and Anti-Clone Functions FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ISO 14443 - 2 Type B Air Interface Compliant ISO 14443 - 3 Type B Frame Format
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56MHz
847kHz
64-bit
4096-bit
40-Year
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PDF
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Untitled
Abstract: No abstract text available
Text: 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR S C A S 1 7 8 - D 3 9 9 0 , D E C E M B E R 1991 - R E V IS E D A P R I L 1 9 9 3 Inputs Are TTL-Voltage Compatible Asynchronous Clear Fully Independent Clock Circuit Simplifies Use
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OCR Scan
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74ACT11867
500-mA
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PDF
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74ACT11867
Abstract: BOX655303
Text: 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178 - D3990, DECEMBER 1991 - REVISED APRIL 1993 DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Asynchronous Clear Fully Independent Clock Circuit Simplifies Use Flow-Through Architecture Optimizes
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OCR Scan
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74ACT11867
SCAS178
D3990,
500-mA
74ACT11867
D10371D
BOX655303
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PDF
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