vhdl code for loop filter of digital PLL
Abstract: vhdl code for frequency divider
Text: LatticeECP2/M sysCLOCK PLL/DLL Design and Usage Guide October 2009 Technical Note TN1103 Introduction This user’s guide describes the clock resources available in the LatticeECP2 and LatticeECP2M™ device architectures. Details are provided for primary clocks, secondary clocks and edge clocks, as well as clock elements
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TN1103
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
vhdl code for loop filter of digital PLL
vhdl code for frequency divider
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Untitled
Abstract: No abstract text available
Text: LatticeECP2/M sysCLOCK PLL/DLL Design and Usage Guide June 2010 Technical Note TN1103 Introduction This user’s guide describes the clock resources available in the LatticeECP2 and LatticeECP2M™ device architectures. Details are provided for primary clocks, secondary clocks and edge clocks, as well as clock elements
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TN1103
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
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lkt 108
Abstract: No abstract text available
Text: DATA SHEET NEC/ MOS INTEGRATED CIRCUIT ADVANCED ATM SONET FRAMER The ^¡PD98404 NEASCOT-P30 is an LSI for ATM applications, which can be used in ATM adapter boards for connecting PCs or workstations to an ATM network and can also be used in ATM hubs and ATM switches. This LSI
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PD98404
NEASCOT-P30
155-Mbps
IR35-203-2
lkt 108
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Untitled
Abstract: No abstract text available
Text: TNETC2080 UNCHANNELIZED MULTI-PROTOCOL COMMUNICATIONS CONTROLLER Compatible With Texas Instruments Tl ATU-C Solution for Asymmetrical Digital Subscriber Line (ADSL) • High-Level Data-Link Control (HDLC) Data Mode - Complies With ISO 3309 - Automatic Flag Detection/Generation
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TNETC2080
SPAS003A-NOVEM
32-Bit
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Untitled
Abstract: No abstract text available
Text: C U B IT Device C eîîB us Switch TXC-05801 DATA SH EE T FEATURES DESCRIPTION • U TO PIA or A LI-25 physical-layer cell interface C U B IT is a single-chip solution fo r im plem enting low -cost ATM m ultiplexing and sw itching system s, based on the CellBus architecture. Such system s are
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TXC-05801
LI-25
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Untitled
Abstract: No abstract text available
Text: DATA SHEET NEC MOS INTEGRATED CIRCUIT ¿ iP D 9 8 4 1 1 ATM QUAD SONET FRAMER T h e ^¡P D 98411 N E A S C O T -P 4 0 is one o f A T M -LA N LSIs and provides the fu n ctio n s o f the T C sub la yer o f the S O N E T /S D H -b a se physical layer o f the ATM protocol spe cifie d by the ATM Forum .
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IR35-363-1
S12953EJ4V0DS00
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24c02 eeprom
Abstract: da qz transistor
Text: TNETX3270 ThunderSWITCH 24/3 ETHERNET™ SWITCH WITH 2410-MBIT/S PORTS AND 310-/100-MBIT/S PORTS S P W S 0 4 3 B - N O VE M B ER 1997 - R EVISED A P R IL 1999 Port Configurations: Twenty-Four 10-Mbit/s Ports - Ports Arranged in Three Groups ot Eight Ports in a Multiplexed Interface
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TNETX3270
2410-MBIT/S
310-/100-MBIT/S
10-Mbit/s
TNETE2008
10-/100-Mbit/s
TNETE2101
24c02 eeprom
da qz transistor
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150L
Abstract: 1N3092 1N3111 1N3288A 1N3296A B-42 weight D0-205AC
Text: Bulletin 12037 International ^Rectifier S E R I E S 45L R , 150K / L / K S ( R ) Stud Version STANDARD RECOVERY DIODES Features • Alloy diode ■ High current carrying capability ■ High voltage ratings up to 1000V ■ High surge current capabilities
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150K/L/KS
20CPC
150K/L
150L
1N3092
1N3111
1N3288A
1N3296A
B-42 weight
D0-205AC
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Untitled
Abstract: No abstract text available
Text: tmän S w it c h x- „ L3M Device Level 3 Mapper TXC-03452B DATA SHEET FEATURES DESCRIPTION ^ • Maps DS3 44.736 Mbit/s or E3 (34.368 Mbit/s) line formats into S D H /S O N E T formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 S P E or STS-1 S P E
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TXC-03452B
16-bit)
TXC-03452B-M
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT 2.4G bps ATM SONET FRAMER The ,uPD98414 NEASCOT-P70 is one of ATM LSIs and provides the functions of the TC sublayer of the SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum.
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uPD98414
NEASCOT-P70â
OC-48c/SDH
STM-16
14242E
0DS00
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LA 42032
Abstract: opti 82C802 HT-88 82C802 82C822 SiS chipset 486 486dlc 82c802g 82C601 amd-486
Text: • ftlIP H M [ iiL IU ll 82C802GP System/Power Management Controller 1.0 * Features - Supports CPUs with L1 write-back feature Processor interface: - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D • - AMD® 486DX, DX2, DXL, DXL2, Plus - Cyrix® DX, DX2, M7
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82C802GP
80486SX,
486DX,
50MHz
33MHz
50MHz
128MB
256rrent
ID000707
LA 42032
opti 82C802
HT-88
82C802
82C822
SiS chipset 486
486dlc
82c802g
82C601
amd-486
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ABT16374A
Abstract: SN54ABT16374A SN74ABT16374A
Text: SN54ABT16374A, SN74ABT16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS _ S C B S 2 0 5 A - M ARCH 1 9 9 3 -R E V IS E D JULY 1994 Members of the Texas Instruments Wldebus Family State-of-the-Art EPIC-IIB™ BICMOS Design
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SN54ABT16374A,
SN74ABT16374A
16-BIT
SCBS205A-
1993-REVISED
MIL-STD-883C,
JESD-17
-32-mA
64-mA
300-mil
ABT16374A
SN54ABT16374A
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MC5246
Abstract: MC-5246 J15H
Text: flXILINX 108-Macrocell CMOS CPLD January, 1997 Version 1.0 Product Specification Features M acrocells can individually be specified for high perfor mance or low power operation by adding attributes to the logic schematic, or declaration statem ents to the behavioral
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108-Macrocell
18-bit
PQ100
100-Pin
PG144
144-Pin
PQ160
160-Pin
BG225
225-Pin
MC5246
MC-5246
J15H
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csr bc7
Abstract: YGV604 at3 block diagram
Text: Y A M A H A ' L S ¿ YGV604 V S G Video Screen Generator • Outline H igh level display functio n ality and a high speed d raw ing function m akes V SG the ideal V D P to control c o n su m er television display screens. A variety o f graphic system s can be easily constructed, for exam ple; video
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YGV604
csr bc7
YGV604
at3 block diagram
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82C801
Abstract: 486DLC/IBM opti 486 chipset
Text: E ili iìj é u n SAHJU 82C802GP System/Power Management Controller 1.0 • Features - Supports CPUs with L1 write-back feature Processor interface: - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D • - AMD® 486DX, DX2, DXL, DXL2, Plus - Cyrix® DX, DX2, M7
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82C802GP
80486SX,
486DX,
50MHz
33MHz
82C801
486DLC/IBM
opti 486 chipset
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Untitled
Abstract: No abstract text available
Text: COBRA Device Constant Bit Rate ATM Adaptation Layer 1 TXC-05427 FEATURES i , —- = DATA SHEET Product Preview = DESCRIPTION COBRA C o nstant Bit Bate ATM Adaptation Layer 1 is a four-channel VLSI device that implements all of the functions needed for circuit emulation over ATM. Both
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TXC-05427
D002QS2
TXC-05427-MB
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Untitled
Abstract: No abstract text available
Text: TNETX3110 ThunderSWITCH 8/3 ETHERNET™ SWITCH WITH EIGHT 10-MBIT/S PORTS AND THREE 10-/100-MBIT/S PORTS SP W S04 7- MARCH 1998 Port Configurations: Eight 10-Mbit/s Ports - Ports Arranged in One Group of Eight Ports in a Multiplexed Interface - Direct Multiplexer Interface to
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TNETX3110
10-MBIT/S
10-/100-MBIT/S
16-Bit/Word,
16-Mbit,
64-Mbit
240-Terminal
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Untitled
Abstract: No abstract text available
Text: PM P r e v ie w In fo r m a tio n Datasheet • ■ T# ■^ PMC-960758 ISSUE 3 PM C -Sierra, Inc. p m 7364Fr e e d m FRAME RELA Y PROTOCOL ENGINE AND DATA LINK MANAGER PM7364 FREEDM FRAME RELAY PROTOCOL ENGINE AND DATALINK MANAGER DATA SHEET Preview Information
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PMC-960758
7364Fr
PM7364
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Untitled
Abstract: No abstract text available
Text: IBM11M32730B IBM11M32730C 32M x 72 DRAM MODULE Features • 32Mx72 Dual Bank Fast Page Mode DIMM System Performance Benefits: -Buffered inputs (except RAS, Data) -Reduced noise (32 Vss/Vcc Pir|s) -4 Byte Interleave enabled -Buffered PDs • Performance:
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IBM11M32730B
IBM11M32730C
32Mx72
110ns
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Untitled
Abstract: No abstract text available
Text: DATA SHEET_ NEC MOS INTEGRATED CIRCUIT /¿ P D 9 8 4 0 1 A ATM SAR CHIP DESCRIPTION The ^¡PD98401A NEASCOT-S15 is a high-performance SAR chip that segments and reassembles ATM cells. This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor,
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PD98401A
NEASCOT-S15â
PD98401A
PD98401,
C10535E)
PD98401AGD-MML:
208-pin
IR35-367-2
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Untitled
Abstract: No abstract text available
Text: L3M Device Level 3 Mapper TXC-03452B DATASHEET FEATURES DESCRIPTION = The L3M maps a DS3 line signal into an STM-1 TUG-3 or STS-3/STS-1 SPE or STS-1 SPE SDH/SONET sig nal. An E3 line signal is mapped into an STM-1 TUG-3 signal only. The L3M provides a TUG-3 formatted signal
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TXC-03452B
TXC-03452B-M
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stb jtag
Abstract: No abstract text available
Text: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT ATM SAR CHIP The ¿ì PD98401A NEASCOT-S15 is a high-performance SAR chip that segments and reassembles ATM cells. This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor,
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uPD98401A
NEASCOT-S15TM)
//PD98401A
tPD98401
tPD98401,
stb jtag
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Untitled
Abstract: No abstract text available
Text: SIEMENS ICs for Communications Analog Network Interface Circuit AN 1C PSB 4450 Version 1.1 PSB 4451 Version 1.1 Preliminary Data Sheet 02.99 DS 4 Revision History: Current Version: 02.99 Previous Version: none Page Page in previous (in current Version Version)
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Untitled
Abstract: No abstract text available
Text: „ tm ä n S w it c h QT1M Device Quad T1 Mapper TXC-04251 x- DATA SHEET FEATURES DESCRIPTION • Add/drop four 1.544 Mbit/s signals from an STS-1, an STS-3/AU-3, or an STM-1 VC-4 The Quad T1 Mapper device is designed for add/drop multiplexer, terminal multiplexer, and dual and single
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TXC-04251
Unit-11s
TU-11s)
positive/nega44
TU-11
TU-11
84-pin
TXC-04011,
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