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    74LS109

    Abstract: ttl 74ls109
    Text: SANYO SEMICONDUCTOR CORP b3E D 7^S7D7b GG111Ö3 7T1 « T S A J O r d e r in g n u m b e r : E N 3 9 1 3 LC74HC109M N o.3913 CMOS H igh-Speed S ta n d ard Logic SA \Y O i Dual J-K Flip-Flop with Set and Reset F e a tu r e s • Dual J-K flip-flop/Falling-edge triggered clock input/A ctive-Low re set input.


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    PDF GG111 MLC74HC109M LC74HC109M 74LS109) 74LS109 ttl 74ls109