L3840
Abstract: L5568 XL78C800 L1S24 L5760 L6240 ls376 L-1344 L6354 78c30
Text: R OHN CORP/ EXEL NELECS 3SE • 7ÖET014 0001353 'r'a b 1°1 07 M ICROELECTRONICS ExetUtnc» D fo E* S ■ REM XL78C800 Multi-Level E2PLDs PIN CO NFIGU RATIO N FEATURES ■ 600-800 Gate Equivalent Logic Com plexity 24 Pin Skinny DIP Type "P 3” Package ■
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ET014
XL78C800
L3840
L5568
XL78C800
L1S24
L5760
L6240
ls376
L-1344
L6354
78c30
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L26XX
Abstract: L2671 L-26-116 L-26-115 26160 L-26-67 L26128
Text: Passive Delay Lines Delay Range 5-450 nsec STYLE L-26 14-pin SIP 10 equally-spaced taps Td/Tr = 5:1 (typ.) For test conditions see page 16. Compatible With Various Logic Systems including TTL and Video Circuits. CONNECTION Total Delay Tolerance = ± 5% or
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14-pin
100PPM/
MIL-D-23859
L-26-87
L-26-57
L-26-117
L-26-157
L-26-88
L-26-58
L-26-158
L26XX
L2671
L-26-116
L-26-115
26160
L-26-67
L26128
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L2612
Abstract: No abstract text available
Text: Passive Delay Lines Delay Range 5-450 nsec STYLE L-26 14-pin SlP 10 equally-spaced taps -r- i /-r j /, \ Td/Tr = 5 i 1 (typ.) For test con ditio ns see page 16. r- Com patible W ith Various Logic Systems including TTL and Video Circuits. CONNECTION GROUND
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14-pin
L-26-84
L-26-114
L-26-155
L-26-85
L-26-55
L-26-115
L-26-156
L-26-86
L-26-56
L2612
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L5472
Abstract: L2688 L5568
Text: r x / i r * ! MICROELECTRONICS XL78C800 Multi-Level E2PLDs PIN CONFIGURATION FEATURES • ■ ■ CLK/I [ Advanced ERASIC Architecture — True gate array style logic integration — From 1 to 42 internal logic levels without using a pin — Eliminates 2-level logic restriction of
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XL78C800
L5472
L2688
L5568
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PDF
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