L25 Incremental
Abstract: 10-32 UNF 2B ov 2094 MS3102R16S-1P 88c30 MS3116J14-19S
Text: L25 Incremental Optical Encoder Mechanical Specifications Shaft Diameter: 1/4” nominal Flat On Shaft: 0.80 long x 0.03 deep Shaft Loading: up to 5 lbs. axial and 8 lbs. radial Shaft Runout: .0005 T.I.R. maximum Starting Torque at 25°C: 0.07 in-oz typical, 0.12 in-oz maximum without sealed
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Original
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MS3116F12-10S,
MS3106F14S-6S
M14/19
MS3116J14-19S,
MS3106F16S-1S
MS3106F18-1S,
MS3106F20-29S
L25 Incremental
10-32 UNF 2B
ov 2094
MS3102R16S-1P
88c30
MS3116J14-19S
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PDF
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XC95288
Abstract: BG352 HQ208 XC9500 X5906 X7131 HQ208I
Text: 1 XC95288 In-System Programmable CPLD December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins
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Original
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XC95288
36V18
HQ208
208-Pin
BG352
352-Pin
XC95288
XC9500
X5906
X7131
HQ208I
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PDF
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PQ160
Abstract: XC9500 XC95216
Text: 1 XC95216 In-System Programmable CPLD August 21, 2001 Version 3.1 1 0* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins
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Original
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XC95216
36V18
PQ160
160-Pin
HQ208
208-Pin
BG352
352-Pin
XC95216
PQ160
XC9500
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PDF
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471 E25
Abstract: PQ160 XC9500 XC95216
Text: XC95216 In-System Programmable CPLD October 28, 1997 Version 2.0 3* Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC95216 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize
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Original
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XC95216
36V18
PQ160
160-Pin
HQ208
208-Pin
BG352
471 E25
XC9500
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PDF
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471 E25
Abstract: XC95216 Family 134-174 PQ160 XC9500 XC95216
Text: 1 XC95216 In-System Programmable CPLD August 21, 2001 Version 3.1 1 0* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins
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Original
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XC95216
36V18
PQ160
160-Pin
HQ208
208-Pin
BG352
352-Pin
XC95216
PQ160
471 E25
XC95216 Family
134-174
XC9500
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PDF
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471 E25
Abstract: PQ160 XC9500 XC95216
Text: 1 XC95216 In-System Programmable CPLD December 4, 1998 Version 3.0 1 12* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins
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Original
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XC95216
36V18
PQ160
160-Pin
HQ208
208-Pin
BG352
352-Pin
XC95216
PQ160
471 E25
XC9500
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PDF
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A23 780-4
Abstract: 471 E25 BG352 HQ208 XC9500 XC95288
Text: XC95288 In-System Programmable CPLD November 12, 1997 Version 2.0 3* Preliminary Product Specification Features MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f • • • • • Where: • • • • • • • • • • • MCHP = Macrocells in high-performance mode
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Original
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XC95288
arcAC25,
HQ208
208-Pin
BG352
352-Pin
XC95288
A23 780-4
471 E25
XC9500
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PDF
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xc95216
Abstract: 352-BALL
Text: XC95216 In-System Programmable CPLD R DS068 v4.2 April 15, 2005 5 Product Specification Features Description • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4,800 usable gates Up to 166 user I/O pins 5V in-system programmable
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Original
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XC95216
DS068
36V18
352-BALL
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PDF
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xc95288
Abstract: BG352 XC95288-20HQ208C XC95288-20HQ208
Text: XC95288 In-System Programmable CPLD R DS069 v4.0 June 18, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable
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Original
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XC95288
DS069
36V18
p352-ball
208-pin
352-ball
352-ball
BG352
XC95288-20HQ208C
XC95288-20HQ208
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PDF
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XC95288
Abstract: BG352 HQ208 XC9500 n439
Text: XC95288 In-System Programmable CPLD R DS069 v4.1 August 21, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable
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Original
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XC95288
DS069
36V18
BG352
352-ball
XC95288-20HQ208I
HQ208
208-pin
XC95288-20BG352I
BG352
HQ208
XC9500
n439
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PDF
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XC95288
Abstract: Marking af1 AF24 marking
Text: XC95288 In-System Programmable CPLD R DS069 v4.2 April 15, 2005 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable
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Original
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XC95288
DS069
36V18
Marking af1
AF24 marking
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PDF
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XC95288
Abstract: PQ208 TQ144 XC9500XL XC95288XL 208pin footprint pqfp 208
Text: XC95288XL High Performance CPLD September 28, 1998 Version 1.0 Advance Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output
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Original
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XC95288XL
XC9500XL
TQ144
144-Pin
PQ208
208-Pin
BG352
352-Pin
-40oC
XC95288XL
XC95288
208pin
footprint pqfp 208
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PDF
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10HQ
Abstract: XC95288 471 E25 HQ208 XC9500
Text: XC95288 In-System Programmable CPLD September 15, 1999 Version 4.0 5* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins
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Original
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XC95288
36V18
HQ208
208-Pin
BG352
352-Pin
XC95288
10HQ
471 E25
XC9500
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PDF
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XC95216
Abstract: XC95216-10PQ160I
Text: XC95216 In-System Programmable CPLD R DS068 v4.0 June 18, 2003 5 Product Specification Features Description • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4,800 usable gates Up to 166 user I/O pins 5V in-system programmable
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Original
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XC95216
DS068
36V18
XC95216-10PQ160I
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PDF
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|
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Untitled
Abstract: No abstract text available
Text: î SS'Np CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 dt) IDT7203 IDT7204 IDT7205 IDT7206 Integrated D<îvice Technology, Inc. FEATURES: DESCRIPTION: • • • • • • • The IDT7203/7204/7205/7206 are dual-port mem ory buff
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OCR Scan
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IDT7203
IDT7204
IDT7205
IDT7206
IDT7203)
IDT7204)
IDT7205)
IDT7206)
770mW
IDT720X
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PDF
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AC1284
Abstract: No abstract text available
Text: KXILINX XC95288 In-System Programmable CPLD April, 1997 Version 1.0 Preliminary Product Specification Features Description • 15 ns pin-to-pin logic delays on all pins • • • • fcNT t ° MHz 288 macrocells with 6,400 usable gates Up to 192 user I/O pins
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OCR Scan
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XC95288
36V18
HQ208
208-Pin
BG352
352-Pin
XC95288
AC1284
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PDF
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Untitled
Abstract: No abstract text available
Text: flX IU N X XC95286 In-System Programmable CPLD November 12, 1997 Version 2.0 Preliminary Product Specification Features MC h p (1.7) + MC lp (0.9) + MC (0.006 m A/M Hz) f • 15 ns pin-to-pin logic delays on all pins Where: • • • • fcNT to MHz 288 macrocells with 6,400 usable gates
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OCR Scan
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XC95286
36V18
XC95288
HQ208
208-Pin
BG352
352-Pin
XC95288
|
PDF
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XC95288
Abstract: No abstract text available
Text: flXIUNX XC95288 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fcN T 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins
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OCR Scan
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XC95288
36V18
HQ208
208-Pin
BG352
352-Pin
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PDF
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F25-F26
Abstract: No abstract text available
Text: flXILINX XC95288 In-System Programmable CPLD N o vem b er 12, 1997 V ersion 2.0 Preliminary Product Specification Features MCHp (1.7) + MC lp (0.9) + MC (0.006 mA/MHz) f • 15 ns pin-to-pin logic delays on all pins • fcNT 95 MHz • 288 macrocells with 6,400 usable gates
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OCR Scan
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XC95288
36V18
HQ208
208-Pin
BG352
352-Pin
F25-F26
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PDF
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XC95216
Abstract: No abstract text available
Text: EXILINX XC95216 In-System Programmable CPLD October 28, 1997 Version 2.0 Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fQNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins
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OCR Scan
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XC95216
36V18
PQ160
160-Pin
HQ208
208-Pin
BG352
352-Pin
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PDF
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XC95288
Abstract: No abstract text available
Text: flXIU N X XC95286 In-System Programmable CPLD October 28, 1997 Version 2.0 Preliminary Product Specification Features MC h p (1.7) + MC lp (0.9) + MC (0.006 m A/M Hz) f • 15 ns pin-to-pin logic delays on all pins Where: • • • • fcNT to MHz 288 macrocells with 6,400 usable gates
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OCR Scan
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XC95286
36V18
boundary-scaE15,
XC95288
HQ208
208-Pin
BG352
352-Pin
XC95288
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PDF
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Untitled
Abstract: No abstract text available
Text: flX IU N X XC95216 In-System Programmable CPLD October 28, 1997 Version 2.0 Product Specification Features Power Management • 10 ns pin-to-pin logic delays on all pins • fcNT to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins
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OCR Scan
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XC95216
36V18
PQ160
160-Pin
HQ208
208-Pin
BG352
352-Pin
XC95216
PQ160
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PDF
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Untitled
Abstract: No abstract text available
Text: flXIUNX XC95216 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • 10 ns pin-to-pin logic delays on all pins • fcN T to 111 MHz • • • 216 macrocells with 4800 usable gates Up to 166 user I/O pins
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OCR Scan
|
XC95216
36V18
PQ160
160-Pin
HQ208
208-Pin
BG352
352-Pin
PQ160
HQ208
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PDF
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Untitled
Abstract: No abstract text available
Text: flXIUNX XC95288XL High Performance CPLD September 28,1998 Version 1.0 Advance Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depend ing on the system frequency, design application and output
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OCR Scan
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XC95288XL
144-pin
208-pin
352-pin
54-input
TQ144
PQ208
BG352
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PDF
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