CDC2510A
Abstract: KMM377S6427T1GL
Text: SDRAM MODULE Preliminary KMM377S6427T1 Revision History Revision 3 May 1998 - CLK Input Cap. is added by PLL Input Cap. (27pF) Revision 4 (July 1998) - "REGE" description is changed. REV. 4 July 1998 Preliminary KMM377S6427T1 SDRAM MODULE KMM377S6427T1 SDRAM DIMM (Intel 1.0 ver. Base)
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KMM377S6427T1
KMM377S6427T1
64Mx72
64Mx4,
64Mx4
400mil
18-bits
CDC2510A
KMM377S6427T1GL
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CS5555
Abstract: U555C CDC2510A
Text: Preliminary KMM377S6427T1 SDRAM MODULE KMM377S6427T1 SDRAM DIMM Intel 1.0 ver. Base 64Mx72 SDRAM DIMM with PLL & Register based on Stacked 64Mx4, 4Banks 4K Ref., 3.3V SDRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM377S6427T1 is a 64M bit x 72 Synchro
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KMM377S6427T1
KMM377S6427T1
64Mx72
64Mx4,
64Mx4
400mil
18-bits
24-pin
CS5555
U555C
CDC2510A
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KMM377S6427T1-GL
Abstract: No abstract text available
Text: SDRAM MODULE Preliminary KMM377S6427T1 Revision History Revision 3 May 1998 - CLK Input Cap. is added by PLL Input Cap. (27pF) REV. 3 May ’98 ELECTRONICS Preliminary KMM377S6427T1 SDRAM MODULE KMM377S6427T1 SDRAM DIMM (Intel 1.0 ver. Base) 64MX72 SDRAM DIMM with PLL & Register based on Stacked 64Mx4, 4Banks 4K Ref., 3.3V SDRAMs with SPD
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OCR Scan
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KMM377S6427T1
KMM377S6427T1
64MX72
64Mx4,
64Mx4
400mJ
18-bits
KMM377S6427T1-GL
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Untitled
Abstract: No abstract text available
Text: SDRAM MODULE Preliminary KMM377S6427T1 Revision History Revision 3 May 1998 - CLK input Cap. is added by PLL Input Cap. (27pF) Revision 4 (July 1998) - "REGE" description is changed. REV. 4 July 1998 Preliminary KMM377S6427T1 SDRAM MODULE KMM377S6427T1 SDRAM DIMM (Intel 1.0 ver. Base)
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OCR Scan
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KMM377S6427T1
KMM377S6427T1
KMM377S6427T1-G8
125MHz
64Mx4
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