radar detector detector 10-25 ghz
Abstract: A7- B14 Radar Warning Receiver 6 pin DCI DCI circuit diagram ADF4350 TCI-1-13M AD9129 AD9129-MIX-EBZ nsd 102
Text: Preliminary Technical Data FEATURES DAC Update Rate of up to 5.6 GSPS Direct RF Synthesis @ 2.8 GSPS Data Rate DC-to-1.4 GHz in Baseband Mode DC-to-1.0 GHz in 2x Interpolation Mode 1.4 to 4.2 GHz in Mix-Mode Bypassable 2x Interpolation Excellent Dynamic performance
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11-/14-Bit,
AD9119/AD9129
AD9129
14-bit
AD9119
11-bit
radar detector detector 10-25 ghz
A7- B14
Radar Warning Receiver
6 pin DCI
DCI circuit diagram
ADF4350
TCI-1-13M
AD9129
AD9129-MIX-EBZ
nsd 102
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ep4cgx30f484
Abstract: EP4CE115 CYIV-5V1-1 EP4CGX EP4CE55 EP4CE15 sigma delta lcd screen lvds 40 pin diagram ep4ce22 ep4ce40
Text: Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.5 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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IBM0418A41NLAB
Abstract: IBM0418A81NLAB IBM0436A41NLAB IBM0436A81NLAB
Text: IBM0436A41NLAB IBM0418A41NLAB IBM0418A81NLAB IBM0436A81NLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM . Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • Registered outputs • 30 Ω drivers
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IBM0436A41NLAB
IBM0418A41NLAB
IBM0418A81NLAB
IBM0436A81NLAB
256Kx36
512Kx18)
128Kx36
256Kx18)
crrL3325
IBM0418A41NLAB
IBM0436A81NLAB
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IS61QDB22M36
Abstract: D0-35 IS61QDB24M18
Text: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . A May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Two echo clocks (CQ and CQ) that are delivered
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IS61QDB22M36-300M3
IS61QDB22M36-300M3L
IS61QDB24M18-300M3
IS61QDB24M18-300M3L
IS61QDB22M36-250M3
IS61QDB22M36-250M3L
IS61QDB24M18-250M3
IS61QDB24M18-250M3L
IS61QDB22M36-200M3L
IS61QDB24M18-200M3L
IS61QDB22M36
D0-35
IS61QDB24M18
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IS61DDB21M36
Abstract: 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI
Text: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . I May 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late
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oDDB22M18-250M3L
1Mx36
2Mx18
IS61DDB21M36
61DDB22M18
IS61DDB22M18-300M3L
IS61DDB22M18
IS61DDB22M18-250M3LI
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D0-35
Abstract: IS61QDB42M36 IS61QDB42M36-300M3 IS61QDB44M18 IS61QDB44M18-300M3
Text: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 4) Synchronous SRAMs 7 Q . May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.
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IS61QDB42M36-300M3
IS61QDB44M18-300M3
IS61QDB42M36-250M3
IS61QDB44M18-250M3
2Mx36
4Mx18
D0-35
IS61QDB42M36
IS61QDB42M36-300M3
IS61QDB44M18
IS61QDB44M18-300M3
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IS61QDB41M36
Abstract: 61QDB41M36 IS61QDB41M36-250M3L D0-35 IS61QDB41M36-250M3 IS61QDB42M18
Text: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . I April 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.
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IS61QDB41M36-250M3
IS61QDB41M36-250M3L
IS61QDB41M36-200M3
IS61QDB42M18-200M3
1Mx36
2Mx18
IS61QDB41M36
61QDB41M36
IS61QDB41M36-250M3L
D0-35
IS61QDB41M36-250M3
IS61QDB42M18
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IBM0418A8ACLAB
Abstract: IBM0436A4ACLAB IBM0436A8ACLAB IBM0418A4ACLAB
Text: . IBM0418A4ACLAB IBM0436A8ACLAB Preliminary IBM0418A8ACLAB IBM0436A4ACLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25 Micron CMOS technology
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IBM0418A4ACLAB
IBM0436A8ACLAB
IBM0418A8ACLAB
IBM0436A4ACLAB
256Kx36
512Kx18)
128Kx36
256Kx18)
crlh3320
IBM0418A8ACLAB
IBM0436A4ACLAB
IBM0436A8ACLAB
IBM0418A4ACLAB
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IBM0418A11NLAA
Abstract: IBM0436A11NLAA
Text: . Preliminary IBM0436A11NLAA IBM0418A11NLAA 32Kx36 & 64Kx18 SRAM Features • 32Kx36 or 64Kx18 organizations • Registered Outputs • 0.25 Micron CMOS technology • 30 Ohm Drivers • Synchronous Pipeline Mode of Operation with Self-Timed Late Write • Common I/O
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IBM0436A11NLAA
IBM0418A11NLAA
32Kx36
64Kx18
32Kx36
nrrL3325
IBM0418A11NLAA
IBM0436A11NLAA
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IBM0418A4ANLAB
Abstract: IBM0418A8ANLAB IBM0436A4ANLAB IBM0436A8ANLAB
Text: . Preliminary IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25µ CMOS technology • Synchronous Register-Latch Mode of Operation
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IBM0418A4ANLAB
IBM0418A8ANLAB
IBM0436A8ANLAB
IBM0436A4ANLAB
256Kx36
512Kx18)
128Kx36
256Kx18)
crlL3325
IBM0418A8ANLAB
IBM0436A4ANLAB
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IBM0418A41XLAB
Abstract: IBM0418A81XLAB IBM0436A41XLAB IBM0436A81XLAB
Text: . Preliminary IBM0418A81XLAB IBM0436A81XLAB IBM0418A41XLAB IBM0436A41XLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25 Micron CMOS technology
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IBM0418A81XLAB
IBM0436A81XLAB
IBM0418A41XLAB
IBM0436A41XLAB
256Kx36
512Kx18)
128Kx36
256Kx18)
crrh2516
IBM0418A41XLAB
IBM0418A81XLAB
IBM0436A41XLAB
IBM0436A81XLAB
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RT3PE600L
Abstract: RT3PE3000L AES-128 PAC10 LG484 ProASICPLUS Flash Family FPGAs Advanced v0.1
Text: Advance v0.1 Radiation-Tolerant ProASIC3 Low-Power SpaceFlight Flash FPGAs with Flash*Freeze Technology Features and Benefits • High-Performance, Low-Skew Global Network • Architecture Supports Ultra-High Utilization MIL-STD-883 Class B Qualified Packaging
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MIL-STD-883
RT3PE600L
RT3PE3000L
AES-128
PAC10
LG484
ProASICPLUS Flash Family FPGAs Advanced v0.1
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Untitled
Abstract: No abstract text available
Text: TLK3118 Redundant XAUI Transceiver www.ti.com • • • • • • • • • • • Fabricated in Advanced 130-nm CMOS Technology Package: Small Footprint 21x21mm, 400-Ball, Fine Pitch 1mm PBGA TLK3118 TDP/N[3:0]0 TCLK TD(31.0) TC(3.0) RCLK RD(31.0)
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TLK3118
130-nm
21x21mm,
400-Ball,
10-Gbps
3ae-2002
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A3PE3000L FG484
Abstract: Actel pdf on radio emitter A3PE3000L FG144 FG256 FG324 FG484 PQ208 TDP 245 Y
Text: v1.3 ProASIC3L Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • Dramatic Reduction in Dynamic and Static Power Savings • 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power • Low Power Consumption in Flash*Freeze Mode Allows for
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130-nm,
A3PE3000L FG484
Actel pdf on radio emitter
A3PE3000L
FG144
FG256
FG324
FG484
PQ208
TDP 245 Y
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AFS600-FG256
Abstract: zo 103 ma 75 607 A54 ZENER flashpro3 schematic mark AT0 Unipolar PC atx 400 P4 power supply diagram zener Diode B23 PQ208 QN108 QN180
Text: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
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130-nm,
128-Bit
AFS600-FG256
zo 103 ma 75 607
A54 ZENER
flashpro3 schematic
mark AT0
Unipolar PC atx 400 P4 power supply diagram
zener Diode B23
PQ208
QN108
QN180
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TLK3114SA
Abstract: P802 TLK3104SA tca 271
Text: TLK3114SA 10ĆGbps XAUI Transceiver Data Manual November 2006 MSDS Multimedia SLLS529D IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TLK3114SA
10Gbps
SLLS529D
TLK3114SA
P802
TLK3104SA
tca 271
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CAT16-LV4F12
Abstract: PAC10 RAM512X18
Text: 2 – ProASIC3E DC and Switching Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA
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AES-128
Abstract: FG256 FG484
Text: v2.0 IGLOOe Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power
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130-nm,
AES-128
FG256
FG484
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A54 ZENER
Abstract: AFS600-FG256 mark AT0 QN108 CORE8051 bipolar ROM
Text: v2.0 Actel Fusion Family of Mixed-Signal FPGAs Features and Benefits In-System Programming ISP and Security High-Performance Reprogrammable Flash Technology Advanced Digital I/O • • • • • Secure ISP with 128-Bit AES via JTAG • FlashLock® to Secure FPGA Contents
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128-Bit
130-nm,
A54 ZENER
AFS600-FG256
mark AT0
QN108
CORE8051
bipolar ROM
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15-V
Abstract: SN74HSTL162822
Text: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series
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SN74HSTL162822
14-BIT
28-BIT
SCES091A
15-V
SN74HSTL162822
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1 pF ceramic capacitor C00 1PC
Abstract: IBM3229P2035 PRS64G SA-12E pqc-2
Text: IBM Packet Routing Switch Serial Interface Converter Datasheet Preliminary January 14, 2002 Copyright and Disclaimer Copyright International Business Machines Corporation 1999, 2000, 2001, 2002 All Rights Reserved Printed in the United States of America, January 2002
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0m02
Abstract: 4G TECHNOLOGY ndi2 F880 IBM3221L0572
Text: â IBM Packet Routing Switch PRS28.4G Version 1.7 Datasheet â Copyright and Disclaimer Copyright International Business Machines Corporation 1999, 2000, 2001. All Rights Reserved Printed in the United States of America February 2001 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both.
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PRS28
IBM3209K4060
IBM3221L0572.
0m02
4G TECHNOLOGY
ndi2
F880
IBM3221L0572
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P09N03
Abstract: No abstract text available
Text: PRELIMINARY PMC-Sierra, Inc. PM9311/2/3/5 ETT1 CHIP SET Data Sheet PMC-2000164 ISSUE 1 ENHANCED TT1™ SWITCH FABRIC PM9311/2/3/5 Enhanced TT1 Chip Set Enhanced TT1 Switch Fabric Datasheet Preliminary: April 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PM9311/2/3/5
P09N03
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Untitled
Abstract: No abstract text available
Text: I = = = = •= Preliminary IBM0418A81QLAA IBM0418A41 QLAA IBM0436A81QLAA IBM0436A41QLAA 8Mb 256Kx36 & 512x18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 256K x 36 or 512K x 18 organizations • Registered Outputs • 128K x 36 or 256K x 18 organizations
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IBM0418A81QLAA
IBM0418A41
IBM0436A81QLAA
IBM0436A41QLAA
256Kx36
512x18)
128Kx36
256Kx18)
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