Contextual Info: fax id: 6147 U Itra371 28V UltraLogic 3.3V 128-Macrocell ISR™ CPLD • High speed Features — fM a x = 1 2 5 M H z 1 2 8 m a c r o c e l l s in e i g h t l o g i e b l o e k s — t PD = 1 0 n s 3.3V In-System R e p ro g ra m m a b le ISR™ — t s = 5. 5 n s

Contextual Info: • ■ J ^ m n r n n PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

O16I

Abstract: 7256P 99L0
Contextual Info: PREUM INAm Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability

Contextual Info: PREUM INAm Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™CLPD — tPD = 10 ns Features — ts = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: . „ n « Ultra37128V PRELIMINARY UltraLogic 3.3V 128-Macrocell ISR™CLPD — tPD = 10 ns Features — ts = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming

ncl016

Contextual Info: •gg P R E L IM IN A R Y ^^^B88888888888888888888SSi^ Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 n s • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6.5 ns Product-term clocking

11J2

Contextual Info: . : f j .T-iT-r-r-PRELIMINARY Y Ultra37256V - H UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 ns • 256 macrocells in sixteen logic blocks — tc o = 6.5 ns • 3.3V In-System Reprogrammable™ ISR™

Contextual Info: . _ n « PRELIMINARY Ultra37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming