MiFare DESFire EV1 8k
Abstract: Mifare protocol AN10833 AN 130830 AN-130830 Mifare plus Mifare Desfire protocol Mifare plus protocol Mifare Plus X 4K UID 7 Byte Mifare ultralight C
Text: AN10833 MIFARE Type Identification Procedure Rev. 3.0 — 18 May 2009 018430 Application note PUBLIC Document information Info Content Keywords MIFARE, ISO/IEC 14443 Abstract This document describes how to differentiate between the members of the MIFARE card IC family. ISO/IEC 14443-3 describes the initialization
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AN10833
AN10833
MiFare DESFire EV1 8k
Mifare protocol
AN 130830
AN-130830
Mifare plus
Mifare Desfire protocol
Mifare plus protocol
Mifare Plus X 4K UID 7 Byte
Mifare ultralight C
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AK8975
Abstract: BMP085 Bosch BMP085 magnetometer ak8975 ITG-3200 AK8957 AKM AK8975 BMA150 gyroscope bosch atmel 924
Text: AVR4016: Sensors Xplained Software Users Guide Features • • • • Hardware-independent C language interfaces for sensor devices Conversion to standard units for all measurement types Device drivers for a variety of MEMS-based sensors Easy-to-use configuration and initialization
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AVR4016:
016A-AVR-01/11
AK8975
BMP085
Bosch BMP085
magnetometer ak8975
ITG-3200
AK8957
AKM AK8975
BMA150
gyroscope bosch
atmel 924
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Si8421A
Abstract: Si8420B Si8421B Si8410B Si8410 Si8420 Si8421 VDE0884 SI8420-B-IS Si8420-B
Text: Si8410/20/21 S INGLE A N D D UAL -C HANNEL D IGITAL I SOLATORS Features High-speed operation Pin Assignments 2500 VRMS isolation DC – 150 Mbps Narrow Body SOIC Transient Immunity Low propagation delay >25 kV/µs <10 ns DC correct No start-up initialization required
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Si8410/20/21
Si841x
Si842x
Si8421A
Si8420B
Si8421B
Si8410B
Si8410
Si8420
Si8421
VDE0884
SI8420-B-IS
Si8420-B
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Untitled
Abstract: No abstract text available
Text: CDCF5801A www.ti.com SCAS816 – MARCH 2006 CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT FEATURES • • • • • • • • • • • • • Low-Jitter Clock Multiplier: x1, ×2, ×4, ×8 Fail-Safe Power Up Initialization Programmable Bidirectional Delay Steps of
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CDCF5801A
SCAS816
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Untitled
Abstract: No abstract text available
Text: April 4, 2013 C8051F41x Revisions A-F Errata Hardware Errata Erratum # H1 H2 H3 Title XTLVLD is Incorrect Port Pin Overvoltage Clock Glitch During the Clock Multiplier Initialization Sequence Impact Minor Minor Minor Status Affected Revisions Fixed Revision
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C8051F41x
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M52235EVB
Abstract: Bean tn265 M5222
Text: Technical Note TN265 Using the Device Initialization and Processor Expert with CodeWarrior Development Studio for ColdFire Architectures v7.0 By: Alfredo Soto and Oscar Gueta Introduction This document demonstrates using Processor Expert embedded beans for a ColdFire microcontroller
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TN265
32-bit
M52235EVB
Bean
tn265
M5222
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Si8420
Abstract: Si8410 Si8421 VDE0884 SI8410-C-IS
Text: Si8410/20/21 S INGLE & D UAL - C HANNEL D IGITAL I SOLATORS Features High-speed operation Pin Assignments 2500 VRMS isolation DC – 150 Mbps Narrow Body SOIC Transient Immunity Low propagation delay >25 kV/µs <10 ns DC correct No start-up initialization required
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Si8410/20/21
Si841x
Si842x
Si8420
Si8410
Si8421
VDE0884
SI8410-C-IS
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Untitled
Abstract: No abstract text available
Text: ESMT M13S128168A Operation temperature condition -40°C~85°C Revision History Revision 1.0 03 Jan. 2007 - Original Revision 1.1 (19 Mar. 2008) - Add BGA package - Modify the waveform of Power up & Initialization Sequence - Modify the θ value of TSOPII package dimension
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M13S128168A
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MC68HC11
Abstract: EB292 M68HC11EVBU MC68HC11EVBU DSA003656 Buffalo monitor
Text: Order this document by EB292/D Motorola Semiconductor Engineering Bulletin EB292 Initialization Considerations When Moving from the BUFFALO Monitor to a Standalone MC68HC11 By Janet M. Snyder Austin, Texas General Information Analog-to-digital A/D convertor code written under the BUFFALO
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EB292/D
EB292
MC68HC11
MC68HC11
EB292
M68HC11EVBU
MC68HC11EVBU
DSA003656
Buffalo monitor
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XC17000
Abstract: XC3000 XC4000 XC2000 XC3000A XC3100 XC3100A XC4000A XC4000D XC4000H
Text: Configuration Control Pin Connections in T 36 he following recommendations guarantee a well-defined beginning for any FPGA configuration or reconfiguration process — after the initialization and clearing of the configuration memory in all FPGAs has been completed, and the
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XC17000d
XC17000
XC17000
XC3000
XC4000
XC2000
XC3000A
XC3100
XC3100A
XC4000A
XC4000D
XC4000H
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transistor c380
Abstract: Motorola MPC556 transistor c388 c1781 DE C308 mpc556 transistor c114 diagram transistor c114 diagrams transistor c118 transistor c144
Text: SECTION 5 UNIFIED SYSTEM INTERFACE UNIT The unified system interface unit USIU of the MPC555 / MPC556 controls system start-up, system initialization and operation, system protection, and the external system bus. The MPC555 / MPC556 USIU functions include the following:
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MPC555
MPC556
0x2C00
0x1880
0x1A80
0x3880
0x3A80
0x3B30
transistor c380
Motorola MPC556
transistor c388
c1781
DE C308
transistor c114 diagram
transistor c114 diagrams
transistor c118
transistor c144
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AVR block diagram
Abstract: AT94K codevision
Text: AVR-FPGA Interface Design 2 Features • Initialization and Use of AVR-FPGA Interface and Interrupts • Initialization and Use of the Shared Dual-port SRAM • Full Source Code for AVR Microcontroller and FPGA Included Programmable SLI AT94K Description
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AT94K
AT94K
doc2325
11/01/xM
AVR block diagram
codevision
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Untitled
Abstract: No abstract text available
Text: Si8410/20/21 5 kV Si8422/23 (2.5 & 5 kV) L O W - P OWER, S INGLE AND D U A L - C HANNEL D IGITA L I S O L A T O R S Features High-speed operation DC to 150 Mbps No start-up initialization required Wide Operating Supply Voltage: 2.6–5.5 V
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Si8410/20/21
Si8422/23
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DS2151
Abstract: DS2153
Text: DS2151/53 APPLICATION NOTE Programming, Initialization March 12, 1996 GENERAL INITIALIZATION FOR THE DS2151 AND DS2153 After power-up, when supplies and clocks have stabilized, internal registers must be initialized. It is a good idea to clear, set to 00H, ALL R/W registers. Certain registers have bits which control special test modes and features which
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DS2151/53
DS2151
DS2153
DS2151:
DS2153:
DS2153
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DSA00359816
Abstract: AT94K 32 Bit loadable counter
Text: AVR-FPGA Interface Design 3 Features • Initialization and Use of AVR-FPGA Interface and Interrupts • Initialization and Use of the Shared Dual-port SRAM • Full Source Code for AVR Microcontroller and FPGA Included Programmable SLI AT94K Description
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AT94K
AT94K
doc2326
11/01/xM
DSA00359816
32 Bit loadable counter
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DIAGRAM pal 005a
Abstract: pal 005a
Text: Preliminary a COM’L PAL24R10-10 Series Advanced Micro Devices 10 ns 28-pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • 10 ns m axim um propagation delay Power-up reset for initialization ■ f MAx = 55.5 MHz Register preload for testability
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PAL24R10-10
28-pin
28-pln
24L10,
24R10,
PAL24L10-10,
PAL24R10-10,
PAL24R8-10,
DIAGRAM pal 005a
pal 005a
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30C162
Abstract: 12x10 character TRANSISTOR SMD MARKING CODE kh "character rom" siemens S43 SMD marking code AE SMD Transistor siemens flash smd marking KH 235L P-LCC-68-1
Text: MEGATEXT and MEGATEXT PLUS ICs SDA 5273 / SDA 5275 SDA 5273-2 / SDA 5275-2 Revision History: 06.97 Previous Releases: 11.96 Page Subjects changes since last revision 20 Now also covers SDA 5275-2 and SDA 5273-2 versions; Reset/chip initialization update
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P-SDIP-52-1
30C162
12x10 character
TRANSISTOR SMD MARKING CODE kh
"character rom" siemens
S43 SMD
marking code AE SMD Transistor
siemens flash
smd marking KH
235L
P-LCC-68-1
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sy6520
Abstract: pia 6820 sy6820 MC6820 PIA 6820 PIA D6520 pia MC6820 SY6520a mc6820 Synertek
Text: SY6520/SY6520A SY6820/SY68B20 Peripheral Interface Adapter PIA Features Autom atic "Handshake" Control of Data Transfers Programmable Interrupt Capability Autom atic Initialization on Power Up 1 and 2 MHz Versions • Direct Replacement for M C6820 • Single +5V Power Supply
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SY6520/SY6520A
SY6820/SY68B20
MC6820
SY6520
9I0MU/9T03AUH
SYC6520/6820
D6520/6820
SYP6520/6820
SYC6520A/68B20
pia 6820
sy6820
MC6820 PIA
6820 PIA
D6520
pia MC6820
SY6520a
mc6820
Synertek
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Untitled
Abstract: No abstract text available
Text: Preliminary COM’L Cl PAL24R10-10 Series Advanced Micro Devices 10 ns 28-pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS Power-up reset for initialization • 10 ns maximum propagation delay ■ f MA x ■ 8 ns maximum from clock input to data output
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PAL24R10-10
28-pin
24L10,
24R10,
PAL24R10-10
PAL24L10-10,
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Untitled
Abstract: No abstract text available
Text: ATS415 Features • Pin-for-PIn Compatible, Functional Superset of PLS1 OS/A and PLUS405 Logic Sequencers • Zero Standby Power of Less than 100 nA Worst Case Power Dissipation at fMAX = 80 mA (Worst Case) • CM OS and TTL Compatible • Programmable Asynchronous Initialization and OE Functions
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ATS415
PLUS405
7258Wsec/cm2
ATS415-16DC
ATS415-16JC
ATS415-16PC
28DW6
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Untitled
Abstract: No abstract text available
Text: CMOS Serial Input 12-Bit DAC AD7543 ANALOG DEVICES FUNCTIO NAL BLOCK DIAGRAM FEATURES Resolution: 12 Bits Nonlinearity: ±1/2LSB Tmin to Tmax Low Gain T.C.: 2ppm/°C typ, 5ppm/°C max Serial Load on Positive or Negative Strobe Asynchronous CLEAR Input for Initialization
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12-Bit
AD7543
10kHz
16-Pin
20-Terminal
AD7543
MIL-M-38510
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PAL20L8
Abstract: MMI PAL 20R4 mmi pal20l8 PAL20R4 MMI TOP MARKING amd part marking PAL20R6 PAL20L8 mmi AMD PAL20L8 LA4490
Text: COM’L: -5/7/B/B-2/A, 10/2 a MIL: -10/12/15/B/A Advanced Micro Devices PAL20R8 Family 24-Pin TTL Programmable Array Logic D ISTINCTIVE CHARACTERISTICS • As fast as 5 ns maximum propagation delay ■ Power-up reset for initialization ■ Popular 24-pin architectures: 20L8,20R8,
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-10/12/15/B/A
PAL20R8
24-Pin
PAL20L8,
PAL20R8,
PAL20R6,
PAL20R4)
PAL20R8-5
PAL20L8
MMI PAL 20R4
mmi pal20l8
PAL20R4
MMI TOP MARKING
amd part marking
PAL20R6
PAL20L8 mmi
AMD PAL20L8
LA4490
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53DA441
Abstract: 53DA442 63DA441 63DA442 D442 Monolithic Memories PROM programming MONOLITHIC MEMORIES PROM
Text: 1 0 2 4 x 4 Diagnostic Registered PROM 5 3 /6 3 D A 4 4 1 5 3 /6 3 D A 4 4 2 Enables and Output Initialization Features/Benefits • Programmable asynchronous output initialization • Three-state outputs with two enables • Provides system diagnostic testing with system
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1024x4
53/63DA441
53/63DA442
24-pln
24-mA
53/63DA442
53/63DA441
53DA441
53DA442
63DA441
63DA442
D442
Monolithic Memories PROM programming
MONOLITHIC MEMORIES PROM
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53DA841
Abstract: 63DA841
Text: 2 0 4 8 x 4 Diagnostic Registered PROM 53D A 841 63D A 841 w ith Asynchronous Enable and Output Initialization Features/Benefits Description • Asynchronous output enable • Programmable asynchronous output Initialization • Provides system diagnostic testing with system
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2048x4
53DA841
63DA841
24-pin
24-mA
diagnosti25
53/63DA841
53DA841
63DA841
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