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    Elite Semiconductor Memory Technology Inc M13S128168A5TG2

    2M X 16 BIT X 4 BANKS DOUBLE DATA RATE SDRAM DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66
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    ComSIT USA M13S128168A5TG2 431
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    Elite Semiconductor Memory Technology Inc M13S128168A5TG2N

    2M X 16 BIT X 4 BANKS DOUBLE DATA RATE SDRAM DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66
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    ComSIT USA M13S128168A5TG2N 40
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    Elite Semiconductor Memory Technology Inc M13S128168A-5TG2N

    Ddr-sdram 128MB 8MX16 200MHZ
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    Win Source Electronics M13S128168A-5TG2N 1,800
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    M13S128168A Datasheets (10)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    M13S128168A Elite Semiconductor Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A Unknown 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-5T Elite Semiconductor Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-5T Elite Semiconductor Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-5TG Unknown 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-6T Elite Semiconductor Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-6T Elite Semiconductor Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-6TG Unknown 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-7.5AB Elite Memory Technology 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Original PDF
    M13S128168A-7.5AB Elite Semiconductor Memory Technology 2M x 16-Bit x 4 Banks Double Data Rate SDRAM Original PDF

    M13S128168A Datasheets Context Search

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    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A Operation temperature condition -40°C~85°C Revision History Revision 1.0 03 Jan. 2007 - Original Revision 1.1 (19 Mar. 2008) - Add BGA package - Modify the waveform of Power up & Initialization Sequence - Modify the θ value of TSOPII package dimension


    Original     		PDF M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESM T M13S128168A 2N Operation Temperature Condition -40°C~85°C DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK )


    Original     		PDF M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A Revision History Revision 0.1 15 Jan. 2002 - Original Revision 0.2 (19 Nov. 2002) -changed ordering information & DC/AC characteristics Revision 0.1 Revision 0.2 M13S128168A - 5T M13S128168A - 6T M13S128168A - 6T M13S128168A - 7.5AB Revision 0.3 (8 Aug. 2003)


    Original     		PDF M13S128168A M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A Revision History Revision 0.1 15 Jan. 2002 - Original Revision 0.2 (19 Nov. 2002) -changed ordering information & DC/AC characteristics Revision 0.1 Revision 0.2 M13S128168A - 5T M13S128168A - 6T M13S128168A - 6T M13S128168A - 7.5AB Revision 0.3 (8 Aug. 2003)


    Original     		PDF M13S128168A M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A Operation temperature condition -40°C~85°C Revision History Revision 1.0 03 Jan. 2007 - Original Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2007 Revision : 1.0 1/48 ESMT M13S128168A Operation temperature condition -40°C~85°C


    Original     		PDF M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESMT Preliminary M13S128168A Revision History Revision 0.1 15 Jan. 2002 - Original Revision 0.2 (19 Nov. 2002) -changed ordering information & DC/AC characteristics Revision 0.1 Revision 0.2 M13S128168A - 5T M13S128168A - 6T M13S128168A - 6T M13S128168A - 7.5AB


    Original     		PDF M13S128168A M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESM T M13S128168A 2N Automotive Grade DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features  Double-data-rate architecture, two data transfers per clock cycle  Bi-directional data strobe (DQS)  Differential clock inputs (CLK and CLK )


    Original     		PDF M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A 2N DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition


    Original     		PDF M13S128168A

    DDR SDRAM

    Abstract: M13S128168A
    Text: ESMT M13S128168A 2N Automotive Grade DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features  Double-data-rate architecture, two data transfers per clock cycle  Bi-directional data strobe (DQS)  Differential clock inputs (CLK and CLK ) 


    Original     		PDF M13S128168A DDR SDRAM M13S128168A

    DDR SDRAM

    Abstract: No abstract text available
    Text: ESMT M13S128168A 2N DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features  Double-data-rate architecture, two data transfers per clock cycle  Bi-directional data strobe (DQS)  Differential clock inputs (CLK and CLK )  DLL aligns DQ and DQS transition with CLK transition


    Original     		PDF M13S128168A DDR SDRAM

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A Revision History Revision 0.1 15 Jan. 2002 - Original Revision 0.2 (19 Nov. 2002) -changed ordering information & DC/AC characteristics Revision 0.1 Revision 0.2 M13S128168A - 5T M13S128168A - 6T M13S128168A - 6T M13S128168A - 7.5AB Revision 0.3 (8 Aug. 2003)


    Original     		PDF M13S128168A M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )


    Original     		PDF M13S128168A

    M13S128168A

    Abstract: No abstract text available
    Text: ESMT M13S128168A DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )


    Original     		PDF M13S128168A M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A 2N DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features  Double-data-rate architecture, two data transfers per clock cycle  Bi-directional data strobe (DQS)  Differential clock inputs (CLK and CLK )  DLL aligns DQ and DQS transition with CLK transition


    Original     		PDF M13S128168A

    CKE 2009

    Abstract: M13S128168A
    Text: ESMT M13S128168A Operation temperature condition -40°C~85°C DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS


    Original     		PDF M13S128168A CKE 2009 M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESMT M13S128168A Revision History Revision 0.1 15 Jan. 2002 - Original Revision 0.2 (19 Nov. 2002) -changed ordering information & DC/AC characteristics Revision 0.1 Revision 0.2 M13S128168A - 5T M13S128168A - 6T M13S128168A - 6T M13S128168A - 7.5AB Revision 0.3 (8 Aug. 2003)


    Original     		PDF M13S128168A M13S128168A

    M13S128168A

    Abstract: No abstract text available
    Text: ESMT M13S128168A Revision History Revision 0.1 15 Jan. 2002 - Original Revision 0.2 (19 Nov. 2002) -changed ordering information & DC/AC characteristics Revision 0.1 Revision 0.2 M13S128168A - 5T M13S128168A - 6T M13S128168A - 6T M13S128168A - 7.5AB Revision 0.3 (8 Aug. 2003)


    Original     		PDF M13S128168A M13S128168A

    M13S128168A

    Abstract: No abstract text available
    Text: ESMT M13S128168A 2N Operation Temperature Condition -40°C~85°C DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features  Double-data-rate architecture, two data transfers per clock cycle  Bi-directional data strobe (DQS)  Differential clock inputs (CLK and CLK )


    Original     		PDF M13S128168A M13S128168A

    Untitled

    Abstract: No abstract text available
    Text: ESM T M13S128168A 2N DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features  Double-data-rate architecture, two data transfers per clock cycle  Bi-directional data strobe (DQS)  Differential clock inputs (CLK and CLK )  DLL aligns DQ and DQS transition with CLK transition


    Original     		PDF M13S128168A

    DDR SDRAM

    Abstract: No abstract text available
    Text: ESMT M13S128168A 2N Operation Temperature Condition -40°C~85°C DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK )


    Original     		PDF M13S128168A DDR SDRAM

    M13S2561616A-5TG

    Abstract: 90-FBGA M12L64164A-7T M13S2561616A -5T M11B416256A-25JP diode 6BG 90FBGA M12L128168A-6TG M12L16161A TSOPII
    Text: Product Selection Guide of ESMT DRAM Density 4Mb Updated Date : 11/06/2006 Organization Description 256Kb*16 EDO DRAM 5V EDO DRAM 5V EDO DRAM 3.3V EDO DRAM 3.3V Refresh 512 512 512 512 Speed 25ns 35ns 35ns 35ns Package Part Number Pb-free Sample MP Now Now


    Original     		PDF 256Kb 40/44L-TSOPII M11B416256A-25JP M11B416256A-35TG M11L416256SA-35JP M11L416256SA-35TG 40L-SOJ 44-40L-TSOPII 128Mb M13S2561616A-5TG 90-FBGA M12L64164A-7T M13S2561616A -5T M11B416256A-25JP diode 6BG 90FBGA M12L128168A-6TG M12L16161A TSOPII

    M13L128168A-4T

    Abstract: No abstract text available
    Text: ESMT M13L128168A Revision History Revision 1.3 -Revise operation voltage. page 5 Revision 1.2 -Changed tWTR from 1 tCK to 2 tCK. Revision 1.1 -Changed absolute max. voltage (VIN, VOUT ,VDD ,VDDQ) from 3.6V to 4.0V Parameter Symbol Value Unit VIN, VOUT -0.5 ~ 4.0


    Original     		PDF M13L128168A M13L128168A-3 M13L128168A-4T