74BCT756

Contextual Info: TEXAS INSTR LOGIC SSE D • Ô=ibl723 G0ÔblS2 1 SN54BCT756, SN74BCT756 OCTAL BUFFERS AND LINE DRIVERS WITH OPEN-COLLECTOR OUTPUTS • 'T 'S Z - 0 7 8N54BCT756 . . . J PACKAGE SN74BCT766. . . DW OR N PACKAGE (TOP VIEW) Open-Collector Version of BCT240 Open-Collector Outputs Drive Bus Lines or

SN74AHCT138

Abstract: 3-line to 8-line
Contextual Info: SN74AHCT138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCLS266 - DECEMBER 1995 D, DB, N, OR PW PACKAGE ftO P VIEW Inputs Are TTL-Voltage Compatible EPIC Enhanced-Performance Implanted CMOS) Process Designed Specifically for High-Speed Memory Decoders and Data Transmission

SN54ABT8652

Abstract: SN74ABT8652
Contextual Info: SN54ABT8652, SN74ABT8652 « SCAN TEST d e v ic e s WITH OCTAL BUS TRANSCEIVERS AND REGISTERS - _ • Members of the Texas Instruments SCOPE Family of Testability Products • Compatible With the IEEE Standard 1149.1-1990 JTAG Test Access Port and

HAI 7203

Abstract: ACT8847 74ACT8847 SN74 multiplier
Contextual Info: TEXAS INSTR LOGIC SSE D 0^1723 GQÖS7G3 7 SN74ACT8847 64-Bit Floating Point Unit • Meets IEEE Standard for Single- and DoublePrecision Formats • Performs Floating Point and Integer Add, Subtract, Multiply, Divide, Square Root, and Compare • 64-Bit IEEE Divide in 11 Cycles, 64-Bit Square

T634

Contextual Info: TEXAS INSTR LOGIC 2SE D 3=1(31723 DOabflQM 7 SN54HCT534, SN74HCT534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS D2804, MARCH 1984-REVISEO SEPTEMBER 1987 Inputs are TTL-Voltage Compatible SN 54H C T634 . . . J PACKAGE SN 74H C T534 . . . DW OR N PACKAGE

SN74ABT16460

Contextual Info: SN54ABT16460, SN74ABT16460 4-T0-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS WITH 3-STATE OUTPUTS S C B S 2 0 7 B - OCTO BER 1992 - REVISED JULY 1994 Members of the Texas Instruments Widebus Family State-of-the-Art EP/C-IIS™ BiCMOS Design Significantly Reduces Power Dissipation

74AC16244

Contextual Info: 74AC16244 16-BIT BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS SC AS120 - D3465, MARCH 1990 - R EVIS ED APRIL 1993 Member of the Texas Instruments Widebus Family DGG OR DL PACKAGE TOP VIEW Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Pin

SN54ABT16843

Abstract: SN74ABT16843
Contextual Info: SN54ABT16843, SN74ABT16843 18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS S C B S 2 2 3 A - O C T O B E R 1992 - R E V IS E D JULY 1994 1CLR [ 1 56 10E [ 2 1Q1 I 3 GND [ 4 1Q2 [ 5 1Q3 6 V CC | 7 55 54 1Q4 I B 49 48 47 15 16 17 18 19 20 21 22 23 description

Texas Instruments TTL handbook

Abstract: D1044 SN74ACT2235 SN74ACT2236
Contextual Info: SN74ACT2235 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148C - DECEMBER 1990 - REVISED SEPTEMBER 1995 • Independent Asynchronous Inputs and Outputs • Low-Power Advanced CMOS Technology • Bidirectional GND FN PACKAGE TO P VIEW

SN74ABT3612

Abstract: B1494
Contextual Info: SN74ABT3612 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY S C BS129F - JULY 1992 - R EVISED FEBRUARY 1996 EFB, FFB, AEB, and AFB Flags Synchronized by CLKB Passive Parity Checking on Each Port Parity Generation Can Be Selected for Each Port

SN54ABT833

Abstract: SN74ABT833
Contextual Info: SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS S C B S 1 9 5 B - FEBR U ARY 1991 - REVISED AP R IL 1995 State-ot-the-Art EPIC-llB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds

ic 74247

Abstract: 74247 22z2 A26c A19C A23C A25C A28C A29C SN74ACT3638
Contextual Info: SN74ACT3638 512 x 32 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 x 32 Clocked FIFOs Buffering Data in Opposite Directions

74AS871

Contextual Info: TEXAS INSTR LOGIC NOTICE SEE ORDER OF DATA FOR ERRATA ESE D • fiU17S3 QOflBTEE 1 ■ T-Vg-0?-0? S N 5 4 A LS 8 70 , SN 5 4AS 8 70 , S N 5 4 A LS 8 71, SN 5 4 A S 8 71 S N 74 A LS 8 70 , S N 74 A S 8 70 , S N 7 4 A L S 8 7 1 , S N 74 A S 8 71 INFORMATION

ic phl 731

Contextual Info: SN74ALS191, SN54ALS191 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS D2661, DECEMBER 19B2 - REVISED M AY 1986 Single Down/Up Count Control Line SN54ALS191 . . J PACKAGE SN74ALS191 D OR N PACKAGE Look-Aheed Circuitry Enhances Speed of Cascaded Counters ITOP VIEWI

1S94

Abstract: DDT7373 SN54BCT373 SN54BCT8373A SN54F373 SN54F37
Contextual Info: SN54BCT8373A SCAN TEST DEVICE WITH OCTAL D-TYPE LATCHES S C B S 044D - JUNE 1990 - REVISED JUNE 1994 • Member of the Texas Instruments SCOPE Family of Testability Products • Octal Test-Integrated Circuit • Functionally Equivalent to SN54F373 and

85a3

Contextual Info: 31E D TEXAS INSTR LOGIC • 6 ^ 1 7 5 3 006^270 0 ■ TII3 54ACT11273,74ACT11273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR T - H _ I q- C T H ) D3443, MARCH 1990-REVISED JULY 1990 54ACT11273 . . . JT PACKAGE 74ACT11273 . . . DW OR NT PACKAGE Inputs are TTL-Voltage Compatible

Contextual Info: 54ACT11000, 74ACT11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SC A S 0 0 2 A - D2957, JU N E 1987 - R E V IS E D A P R IL 1993 54ACT11000. J PA C K A G E 74ACT11000. D O R N PA C K A G E Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes

Contextual Info: 74ACT11646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS061A - 02957. JULY 1987 - REVISED APRIL 1993 DW P A C K A G E TOP VIEW • Independent Registers for A and B Bu ses • Multiplexed Real-Time and Stored Data • Flow-Through Architecture Optimizes

Contextual Info: SN54ALS10A, SN54AS10, SN74ALS10A, SN74AS10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDAS002B - MARCH 1984 - REVISED DECEMBER 1994 • Package Options Include Plastic Small-Outline D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs