GX SERIES Search Results

GX SERIES Result Highlights (5)

Part	Manufacturer	Description
PQU650M-F-COVER	Murata Manufacturing Co Ltd	PQU650M Series - 3x5 Fan Cover Kit, RoHs Medical
11C90DM	Rochester Electronics LLC	11C90 - Prescaler, ECL Series
11C90DM/B	Rochester Electronics LLC	11C90 - Prescaler, ECL Series
11C05DM/B	Rochester Electronics LLC	11C05 - Prescaler, ECL Series
74LS384N	Rochester Electronics LLC	74LS384 - Multiplier, LS Series, 8-Bit

GX SERIES Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
carry select adder Abstract: AGX51002-1 Text: 2. Arria GX Architecture AGX51002-1.2 Transceivers Arria GX devices incorporate up to 12 high-speed serial transceiver channels that build on the success of the Stratix II GX device family. Arria GX transceivers are structured into full-duplex transmitter and	Original	AGX51002-1 carry select adder	PDF
B17C Abstract: frequency divider block diagram simple block diagram for digital clock EP1AGX50DF single phase ups block diagram AGX52001-2 8b10b EP1AGX20CF Text: 1. Arria GX Transceiver Architecture AGX52001-2.0 Introduction Arria GX is a protocol-optimized FPGA family that leverages Altera’s advanced multi-gigabit transceivers. The Arria GX transceiver blocks build on the success of the Stratix II GX family and are optimally	Original	AGX52001-2 8B/10B B17C frequency divider block diagram simple block diagram for digital clock EP1AGX50DF single phase ups block diagram 8b10b EP1AGX20CF	PDF
10-bit-serdes Abstract: K280A B010011 8HBC D243 Text: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.1 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram	Original	SIIGX52002-4 8B/10B 10-bit-serdes K280A B010011 8HBC D243	PDF
EP2SGX60EF Abstract: CEI 23-16 circuit diagram of PPM transmitter and receiver CPRI multi rate HD-SDI over sdh PRBS10 3G-SDI serializer SIIGX52002-4 k307 Text: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.2 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram	Original	SIIGX52002-4 8B/10B EP2SGX60EF CEI 23-16 circuit diagram of PPM transmitter and receiver CPRI multi rate HD-SDI over sdh PRBS10 3G-SDI serializer k307	PDF
simple block diagram for digital clock Abstract: AGX51002-2 cascade shift register prbs generator using vhdl Text: 2. Arria GX Architecture AGX51002-2.0 Transceivers Arria GX devices incorporate up to 12 high-speed serial transceiver channels that build on the success of the Stratix ® II GX device family. Arria GX transceivers are structured into full-duplex transmitter and receiver four-channel groups called	Original	AGX51002-2 simple block diagram for digital clock cascade shift register prbs generator using vhdl	PDF
AN328 Abstract: AP1910 MT47H64M16BT-37E MT47H32M16CC-3 AL1510 EP2SGX90FF1508C3 AL15-10 MT47H64M8CB-3 MT47H64M16 MT47H64M16BT-37E eye Text: AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices October 2009 AN-328-6.0 Introduction This application note provides information about interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria ® GX devices. It includes details about supported modes and	Original	AN-328-6 AN328 AP1910 MT47H64M16BT-37E MT47H32M16CC-3 AL1510 EP2SGX90FF1508C3 AL15-10 MT47H64M8CB-3 MT47H64M16 MT47H64M16BT-37E eye	PDF
Untitled Abstract: No abstract text available Text: 795 FIBER SENSORS Cylindrical Inductive Proximity Sensor Amplifier Built-in GX-U SERIES GX-FU SERIES GX-N SERIES Related Information •■General terms and conditions. F-17 ■■Glossary of terms. P.1386~ ■■Sensor selection guide. P.757~	Original	GX-18MUB-J GX-30MU GX-F30MU-J MS-H12 GX-12MU GX-N12M MS-H18 GX-18MU GX-N18M MS-H30	PDF
texas handbook Abstract: 1008-B Text: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.	Original		PDF
HD-SDI over sdh Abstract: GR-253-CORE PRBS31 SMPTE292M SSTL-15 SSTL-18 PRBS-15 Text: Section I. Arria II GX Device Data Sheet and Addendum This section provides information about the Arria II GX device data sheet and addendum. This section includes the following chapters: • Chapter 1, Arria II GX Device Datasheet ■ Chapter 2, Addendum to the Arria II GX Device Handbook	Original		PDF
Untitled Abstract: No abstract text available Text: Section I. Arria II GX Device Data Sheet and Addendum This section provides information about the Arria II GX device data sheet and addendum. This section includes the following chapters: • Chapter 1, Arria II GX Devices Data Sheet ■ Chapter 2, Addendum to the Arria II GX Device Handbook	Original		PDF
prbs pattern generator using analog verilog Abstract: verilog code of prbs pattern generator port interconnect prbs pattern generator using vhdl vhdl code for 8-bit adder power module hd- 110 vhdl code for crossbar switch Verilog code "1-bit full subtractor" higig protocol overview PRBS altera verilog Text: 2. Stratix II GX Architecture SIIGX51003-2.1 Transceivers Stratix II GX devices incorporate dedicated embedded circuitry on the right side of the device, which contains up to 20 high-speed 6.375-Gbps serial transceiver channels. Each Stratix II GX transceiver block contains	Original	SIIGX51003-2 375-Gbps 152-pin EP2SGX60 prbs pattern generator using analog verilog verilog code of prbs pattern generator port interconnect prbs pattern generator using vhdl vhdl code for 8-bit adder power module hd- 110 vhdl code for crossbar switch Verilog code "1-bit full subtractor" higig protocol overview PRBS altera verilog	PDF
free verilog code of prbs pattern generator Abstract: CPRI multi rate digital alarm clock vhdl code 10 band graphic equalizer CEI 23-16 diode handbook HD-SDI over sdh SDH 209 vhdl code for 16 prbs generator vhdl code for phase frequency detector for FPGA Text: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.	Original		PDF
B17C Abstract: Chapter 3 Synchronization diode handbook SDI SERIALIZER Semiconductor Reference and Application Handbook AGX52001-2 Voltage-controlled oscillator hd-SDI deserializer LVDS EP1AGX50DF Text: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:	Original		PDF
AN-29 Abstract: Power Integrations transformer for top249 TOP244 TOP249 TOP243 TOP246 TOP247 TOPSWITCH TOP248 Text: ® TOPSwitch -GX Flyback Quick Selection Curves Application Note AN-29 Introduction This application note is intended for engineers starting a flyback power supply design with TOPSwitch-GX. It offers a quick method to select the proper TOPSwitch-GX device from	Original	AN-29 AN-29 Power Integrations transformer for top249 TOP244 TOP249 TOP243 TOP246 TOP247 TOPSWITCH TOP248	PDF

SSTL-18 Abstract: No abstract text available Text: Stratix GX November 2002, ver. 1.0 Introduction FPGA Family Data Sheet Preliminary Information The StratixTM GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver	Original		PDF
RTL code for ethernet Abstract: transistor h5c verilog code of prbs pattern generator barrel shifter block diagram free verilog code of prbs pattern generator verilog code for 10 gb ethernet SGX52001-1 SGX52005-1 Text: Section I. Stratix GX Transceiver User Guide This section provides information on the configuration modes for Stratix GX devices. It also includes information on testing, Stratix GX port and parameter information, and pin constraint information. This section includes the following chapters:	Original		PDF
obsai Abstract: EP1AGX50CF484C6 Text: Arria GX Family Press FAQ What is the Arria GX FPGA family? The Arria GX family is comprised of Altera’s 90-nm low cost, transceiver-based FPGAs. The devices are optimized for the mainstream serial protocols from 600 Mbps up to 3.125 Gbps. Five family members range from 21,580 to 90,220 logic elements LEs . The Arria GX family is	Original	90-nm obsai EP1AGX50CF484C6	PDF
TOP243 equivalent Abstract: TOP249 TOP244 TOP246 equivalent topswitch 243Y flyback top249 TOP246 247Y TOP245 TOP244 data Text: ® TOPSwitch -GX Flyback Quick Selection Curves Application Note AN-29 Introduction This application note is intended for engineers starting a flyback power supply design with TOPSwitch-GX. It offers a quick method to select the proper TOPSwitch-GX device from	Original	AN-29 TOP243 equivalent TOP249 TOP244 TOP246 equivalent topswitch 243Y flyback top249 TOP246 247Y TOP245 TOP244 data	PDF
LHF16J06 Abstract: EPC16 0x00010040 Text: 2. Remote System Configuration with Stratix & Stratix GX Devices S52015-3.1 Introduction Altera Stratix® and Stratix GX devices are the first programmable logic devices PLDs featuring dedicated support for remote system configuration. Using remote system configuration, a Stratix or Stratix GX	Original	S52015-3 LHF16J06 EPC16 0x00010040	PDF
vhdl code for 16 prbs generator Abstract: prbs pattern generator using vhdl PRBS10 PRBS altera verilog vhdl code for 8-bit adder Text: 2. Stratix II GX Architecture SIIGX51003-2.2 Transceivers Stratix II GX devices incorporate dedicated embedded circuitry on the right side of the device, which contains up to 20 high-speed 6.375-Gbps serial transceiver channels. Each Stratix II GX transceiver block contains	Original	SIIGX51003-2 375-Gbps 152-pin EP2SGX60 vhdl code for 16 prbs generator prbs pattern generator using vhdl PRBS10 PRBS altera verilog vhdl code for 8-bit adder	PDF
0X001F0000 Abstract: POF Formats Altera 0x00010040 stratus EPC16 LHF16J06 Text: 12. Remote System Configuration with Stratix & Stratix GX Devices S52015-3.1 Introduction Altera Stratix® and Stratix GX devices are the first programmable logic devices PLDs featuring dedicated support for remote system configuration. Using remote system configuration, a Stratix or Stratix GX	Original	S52015-3 0X001F0000 POF Formats Altera 0x00010040 stratus EPC16 LHF16J06	PDF
circuit diagram of full subtractor circuit Abstract: "Fast Cycle RAM" Serial RapidIO Infiniband logic diagram to setup adder and subtractor 32 bit carry select adder code HP lvds connector 40 pin to 30 pin to 7 pin infiniband Physical Medium Attachment SSTL-18 transistor on 4436 Text: Stratix GX March 2003, ver. 1.2 Introduction FPGA Family Data Sheet Preliminary Information The StratixTM GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver	Original		PDF
JESD8-15 Abstract: HSTL standards SSTL-18 class 8 date sheet EIA standards 15-V Text: 10. Selectable I/O Standards in Stratix II and Stratix II GX Devices SII52004-4.6 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices, including: • ■ ■ ■ ■ Stratix II and Stratix II GX I/O	Original	SII52004-4 JESD8-15 HSTL standards SSTL-18 class 8 date sheet EIA standards 15-V	PDF
GX-18H Abstract: GX-30MB GX-30M Text: A m p lifie r b u ilt-in ty p e ^ GX series k Inductive proximity^ r sensors j Wide variation • Ultra small sensor The smallest 03.8mm size GX-3S and GX-3SB in the industry enabling installation anywhere. • Long-distance sensing The non-flush (GX-18H and units suffied by "ML") type is the	OCR Scan	GX-18H protectio12ML GX-12MLB GX-18ML GX-18MLB GX-18H GX-30MB GX-30M	PDF

GX SERIES Search Results

GX SERIES Result Highlights (5)

GX SERIES Datasheets Context Search

carry select adder

B17C

10-bit-serdes

EP2SGX60EF

simple block diagram for digital clock

AN328

Untitled

texas handbook

HD-SDI over sdh

Untitled

prbs pattern generator using analog verilog

free verilog code of prbs pattern generator

B17C

AN-29

SSTL-18

RTL code for ethernet

obsai

TOP243 equivalent

LHF16J06

vhdl code for 16 prbs generator

0X001F0000

circuit diagram of full subtractor circuit

JESD8-15

GX-18H