GX MARK Search Results

GX MARK Result Highlights (6)

Part	Manufacturer	Description
OP249GSZ	Analog Devices	SO-8 MARKED AS \\OP249G\\
DAC08ESZ-REEL	Analog Devices	SO-16 MARKED AS \\DAC08E\\
REF02CSZ	Analog Devices	SO-8 MARKED AS \\REF02C\\
DAC08ESZ	Analog Devices	SO-16 MARKED AS \\DAC08E\\
REF03GSZ	Analog Devices	SO-8 MARKED AS \\REF03G\\
OP221GSZ	Analog Devices	SO-8 MARKED AS \\OP221G\\

GX MARK Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
S82451KX Abstract: s82452kx S82454GX s82453kx 450GX 450KX 82453KX 243109 d655 s-spec Text: Intel 450KX/GX PCIset Specification Update 82454KX/GX PB 82453KX/GX (MC) 82452KX/GX (DP) 82451KX/GX (MIC) Release Date: April 1998 Order Number: 243109-014 The Intel 450KX/GX PCIset may contain design defects or errors known as errata which may cause the product	Original	PDF	450KX/GX 82454KX/GX 82453KX/GX 82452KX/GX 82451KX/GX S82451KX s82452kx S82454GX s82453kx 450GX 450KX 82453KX 243109 d655 s-spec
U042 Abstract: S82454GX 450GX 450KX 82453KX S82451KX 243109 S82451GX 82451KX Text: Intel 450KX/GX PCIset Specification Update 82454KX/GX PB 82453KX/GX (MC) 82452KX/GX (DP) 82451KX/GX (MIC) Release Date: October 1997 Order Number: 243109-012 The 450KX/GX PCIset may contain design defects or errors known as errata which may cause the product to	Original	PDF	450KX/GX 82454KX/GX 82453KX/GX 82452KX/GX 82451KX/GX U042 S82454GX 450GX 450KX 82453KX S82451KX 243109 S82451GX 82451KX
450GX Abstract: S82454GX 3014 LED 82450 S82452GX S82454 3554-1 pciset datasheet S82451GX U056 Text: Intel 450KX/GX PCIset Specification Update 82454KX/GX PB 82453KX/GX (MC) 82452KX/GX (DP) 82451KX/GX (MIC) Release Date: August 1998 Order Number: 243109-015 The Intel 450KX/GX PCIset may contain design defects or errors known as errata which may cause the product	Original	PDF	450KX/GX 82454KX/GX 82453KX/GX 82452KX/GX 82451KX/GX 450GX S82454GX 3014 LED 82450 S82452GX S82454 3554-1 pciset datasheet S82451GX U056
10-bit-serdes Abstract: K280A B010011 8HBC D243 Text: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.1 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram	Original	PDF	SIIGX52002-4 8B/10B 10-bit-serdes K280A B010011 8HBC D243
ddr dimm pinout Abstract: L1238 socket am3 pinout j8510 fairchild aa11 MDIO clause 22 J124 J68 10A intel D915 xcvr Text: Stratix GX Development Board Data Sheet August 2003, ver. 1.1 Designers can use the Stratix GX Development Board to prototype and develop high-speed applications for StratixTM GX and StratixTM FPGAs. Use of this board can shorten the time to market for applicable designs.	Original	PDF	RS-232, ddr dimm pinout L1238 socket am3 pinout j8510 fairchild aa11 MDIO clause 22 J124 J68 10A intel D915 xcvr
EP2SGX60EF Abstract: CEI 23-16 circuit diagram of PPM transmitter and receiver CPRI multi rate HD-SDI over sdh PRBS10 3G-SDI serializer SIIGX52002-4 k307 Text: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.2 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram	Original	PDF	SIIGX52002-4 8B/10B EP2SGX60EF CEI 23-16 circuit diagram of PPM transmitter and receiver CPRI multi rate HD-SDI over sdh PRBS10 3G-SDI serializer k307
AN328 Abstract: AP1910 MT47H64M16BT-37E MT47H32M16CC-3 AL1510 EP2SGX90FF1508C3 AL15-10 MT47H64M8CB-3 MT47H64M16 MT47H64M16BT-37E eye Text: AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices October 2009 AN-328-6.0 Introduction This application note provides information about interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria ® GX devices. It includes details about supported modes and	Original	PDF	AN-328-6 AN328 AP1910 MT47H64M16BT-37E MT47H32M16CC-3 AL1510 EP2SGX90FF1508C3 AL15-10 MT47H64M8CB-3 MT47H64M16 MT47H64M16BT-37E eye
texas handbook Abstract: 1008-B Text: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.	Original	PDF
video transmiter Abstract: hd sdi receiver DDR333 EPC16 MK2069 27mhz transmitter and receiver hd receiver 27mhz transmitter 27mhz receiver 20 pin header connector Text: Stratix GX Video Demonstration Board Data Sheet May 2004, version 1.0 Introduction f The Altera Stratix® GX Video Demonstration Board is an evaluation platform that demonstrates the superior video performance and key features of Altera’s Stratix GX devices. The Stratix GX board and Altera’s	Original	PDF	SMPTE-292M SMPTE-259M video transmiter hd sdi receiver DDR333 EPC16 MK2069 27mhz transmitter and receiver hd receiver 27mhz transmitter 27mhz receiver 20 pin header connector
EP4SGX230 Abstract: EP4SGX180 EP4SGX290 EP4SGX360 EP4SGX70 receiver altLVDS EP4SGX230ES Text: Errata Sheet for Stratix IV GX Devices ES-01022-5.5 Errata Sheet This errata sheet provides updated information about known device issues affecting Stratix IV GX devices. Production Devices for Stratix IV GX Devices Table 1 lists the specific issues and the affected Stratix IV GX production devices.	Original	PDF	ES-01022-5 M9K/M144K EP4SGX230 EP4SGX180 EP4SGX290 EP4SGX360 EP4SGX70 receiver altLVDS EP4SGX230ES
HD-SDI over sdh Abstract: GR-253-CORE PRBS31 SMPTE292M SSTL-15 SSTL-18 PRBS-15 Text: Section I. Arria II GX Device Data Sheet and Addendum This section provides information about the Arria II GX device data sheet and addendum. This section includes the following chapters: • Chapter 1, Arria II GX Device Datasheet ■ Chapter 2, Addendum to the Arria II GX Device Handbook	Original	PDF
Untitled Abstract: No abstract text available Text: Section I. Arria II GX Device Data Sheet and Addendum This section provides information about the Arria II GX device data sheet and addendum. This section includes the following chapters: • Chapter 1, Arria II GX Devices Data Sheet ■ Chapter 2, Addendum to the Arria II GX Device Handbook	Original	PDF
AGX52007-1 Abstract: SSTL-18 Text: 7. External Memory Interfaces in Arria GX Devices AGX52007-1.0 Introduction ArriaTM GX devices support external memory interfaces, including DDR SDRAM, DDR2 SDRAM, and SDR SDRAM. Its dedicated phase-shift circuitry allows the Arria GX device to interface with an external memory	Original	PDF	AGX52007-1 233MHz/466 SSTL-18
free verilog code of prbs pattern generator Abstract: CPRI multi rate digital alarm clock vhdl code 10 band graphic equalizer CEI 23-16 diode handbook HD-SDI over sdh SDH 209 vhdl code for 16 prbs generator vhdl code for phase frequency detector for FPGA Text: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.	Original	PDF

B17C Abstract: Chapter 3 Synchronization diode handbook SDI SERIALIZER Semiconductor Reference and Application Handbook AGX52001-2 Voltage-controlled oscillator hd-SDI deserializer LVDS EP1AGX50DF Text: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:	Original	PDF
EP2AGX125 Abstract: ALTMEMPHY Text: Arria II GX Device Family ES-01025-3.1 Errata Sheet Introduction This errata sheet provides updated information about known device issues affecting Arria II GX devices. Table 1 lists the specific issues and which Arria II GX devices are affected by each	Original	PDF	ES-01025-3 EP2AGX125 ALTMEMPHY
circuit diagram of inverting adder Abstract: KR 108 6621 3.3V Text: Stratix GX FPGA Family Data Sheet December 2004, ver. 2.2 Introduction The Stratix GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver	Original	PDF
b17c Abstract: AGX52001-1 AGX52002-1 PMD 1000 Text: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:	Original	PDF
SSTL-18 Abstract: No abstract text available Text: Stratix GX November 2002, ver. 1.0 Introduction FPGA Family Data Sheet Preliminary Information The StratixTM GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver	Original	PDF
Untitled Abstract: No abstract text available Text: 795 FIBER SENSORS Cylindrical Inductive Proximity Sensor Amplifier Built-in GX-U SERIES GX-FU SERIES GX-N SERIES Related Information •■General terms and conditions. F-17 ■■Glossary of terms. P.1386~ ■■Sensor selection guide. P.757~	Original	PDF	GX-18MUB-J GX-30MU GX-F30MU-J MS-H12 GX-12MU GX-N12M MS-H18 GX-18MU GX-N18M MS-H30
obsai Abstract: EP1AGX50CF484C6 Text: Arria GX Family Press FAQ What is the Arria GX FPGA family? The Arria GX family is comprised of Altera’s 90-nm low cost, transceiver-based FPGAs. The devices are optimized for the mainstream serial protocols from 600 Mbps up to 3.125 Gbps. Five family members range from 21,580 to 90,220 logic elements LEs . The Arria GX family is	Original	PDF	90-nm obsai EP1AGX50CF484C6
AN-247 Abstract: Altera Stratix V AN247 Text: Stratix GX to Mercury Interoperability November 2002, ver. 1.0 Introduction Application Note 247 The introduction of the StratixTM GX device family enables a new level of integration by combining 3.125-gigabits per second Gbps transceivers with a high-performance FPGA core. The Stratix GX family is the	Original	PDF	125-gigabits AN-247 Altera Stratix V AN247
gxb tx_coreclk Abstract: Altera 8b10b Text: Stratix GX FPGA Errata Sheet July 2007, ver. 1.6 Introduction This document addresses transceiver-related known errata for the Stratix GX FPGA family production devices. 1 Receiver Phase Compensation FIFO For more information on Stratix GX device errata, refer to the	Original	PDF	16-bit 20-bit) gxb tx_coreclk Altera 8b10b
LHF16J06 Abstract: EPC16 0x00010040 Text: 2. Remote System Configuration with Stratix & Stratix GX Devices S52015-3.1 Introduction Altera Stratix® and Stratix GX devices are the first programmable logic devices PLDs featuring dedicated support for remote system configuration. Using remote system configuration, a Stratix or Stratix GX	Original	PDF	S52015-3 LHF16J06 EPC16 0x00010040

GX MARK Search Results

GX MARK Result Highlights (6)

GX MARK Datasheets Context Search

S82451KX

U042

450GX

10-bit-serdes

ddr dimm pinout

EP2SGX60EF

AN328

texas handbook

video transmiter

EP4SGX230

HD-SDI over sdh

Untitled

AGX52007-1

free verilog code of prbs pattern generator

B17C

EP2AGX125

circuit diagram of inverting adder

b17c

SSTL-18

Untitled

obsai

AN-247

gxb tx_coreclk

LHF16J06