TXC07900AIBG
Abstract: TXC-07900AIBG TSOP transmitter B020H OED155TM TXC-07900-MB VTXP-6 AU-AIS dk12b EK117
Text: OED155 Device Dual STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07900 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED155, is a dual STM-1 SDH framer and overhead terminator, virtual tributary
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OED155
TXC-07900
TXC-07900-MB,
OED155TM
TXC07900AIBG
TXC-07900AIBG
TSOP transmitter
B020H
OED155TM
TXC-07900-MB
VTXP-6
AU-AIS
dk12b
EK117
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rneg2
Abstract: No abstract text available
Text: QT1F-Plus Device Quad T1 Framer-Plus TXC-03103C DESCRIPTION • D4 SF, ESF including HDLC Link support , and transparent framing modes • Encodes/decodes AMI/B8ZS and forced ones density line codes • Fractional T1 gapped clock • Monitor function for frame pulse, clock and data
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TXC-03103C
TXC-03103C-MB,
rneg2
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TXC-16742
Abstract: EtherPHAST-48 TXC-16742-MC
Text: TM EtherPHAST -48 Pt Device OC-48/STM-16 SONET/SDH Ethernet Mapper TXC-16742 PRODUCT INFORMATION FEATURES APPLICATIONS • 1x STS-48/STM-16 or 4x STS-12/STM-4 framer with TOH processing, 4x 622 LVDS line side interface • 622 MHz Tx side clock synthesizer
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OC-48/STM-16
TXC-16742
TXC-16742-MC,
OC-48/
OC-12
EtherPHAST-48
8B/10B
10B/24x
TXC-16742
TXC-16742-MC
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Cx2829
Abstract: ,national semiconductor Linear brief lb-3
Text: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and
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CX28250
53-byte
28250-DSH-002-A
CX28250
Cx2829
,national semiconductor Linear brief lb-3
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BM1S
Abstract: sonet testbench CP155
Text: SONET/SDH STS-3c/STM-1 Framer MegaCore Function STS3CFRM December 19, 2000; ver. 1.00 Features • ■ ■ ■ ■ ■ ■ Typical Applications Easy-to-use MegaWizard Plug-In generates MegaCore® variants QuartusTM software and OpenCoreTM feature allow place-and-route,
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Untitled
Abstract: No abstract text available
Text: XRT86VX38A 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION JULY 2013 REV. 1.0.0 GENERAL DESCRIPTION The XRT86VX38A is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Shorthual LIU integrated solution featuring R3 technology
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XRT86VX38A
XRT86VX38A
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multiplexing e1 frame to e3 frame
Abstract: S1215P S1215 STM MARKING GR-253 TU12 32xDS1
Text: Product Brief 5 21 S1 UR AM S1215 Amur Deep channelization SONET/SDH to PDH framer and 1K Channels HDLC/ATM/GFP processor Overview SONET/SDH Line Features Tributary Features S1215 (Amur) interfaces with 155Mbps/622Mbps SONET/SDH (1xSTS-12/STM-4, 4xSTS-3/STM-1)
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S1215
155Mbps/622Mbps
1xSTS-12/STM-4,
32xDS1/E1/J1
PB2013
multiplexing e1 frame to e3 frame
S1215P
S1215
STM MARKING
GR-253
TU12
32xDS1
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A23 1101 01A
Abstract: E1-PCM-30 Bt8370KPF RJ48C EE - 19c TRANSFORMER E1-PCM-30 ch chips 65554 RDL2 MC68302 TR-303
Text: Bt8370/75/76 Fully Integrated T1/E1 Framer and Line Interface The Bt8370/75/76 is a family of single-chip transceivers for T1/E1 and Integrated Distinguishing Features Service Digital Network ISDN primary rate interfaces, operating at 1.544 Mbps or 2.048 Mbps. These devices combine a sophisticated framer, transmit and receive slip ! Single-chip T1/E1 framer with short/long
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Bt8370/75/76
Bt8370/75/76
Bt8370
Bt8375
Bt8376
500030B
A23 1101 01A
E1-PCM-30
Bt8370KPF
RJ48C
EE - 19c TRANSFORMER
E1-PCM-30 ch
chips 65554
RDL2
MC68302
TR-303
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BROADCOM "heat sink" 7
Abstract: BCM8110 BCM8111 BCM8501 HSBGA
Text: BCM8501 PRODUCT Brief STS-192c/STM-64c POS/ATM FRAMER AND MAPPER B C M 8 5 0 1 S U M M A R Y F E AT U R E S Provides ATM and Packet over SONET/SDH POS • STS-192c (9.953 Gbps) PHY. Inserts and extracts ATM cells or POS packets into/from • the SONET Synchronous Payload Envelope (SPE).
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BCM8501
STS-192c/STM-64c
STS-192cATM
16-byte
64-byte
16-bit
BCM8501
612-pin
8501-PB01-R-8
BROADCOM "heat sink" 7
BCM8110
BCM8111
HSBGA
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Q-64G
Abstract: 405EP C192 C192X 160GB q80g
Text: PRS Q-80G, PRS C48X, and PRS C192X Switch Fabric PB PRS Q-80G / v0.5 / 10-14-2004 The PRS Q-80G is an integral part of a complete system solution with AMCC's integrated network processor and full-featured traffic manager products nP3700 , framers, PHYs, PowerPC
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Q-80G,
C192X
Q-80G
nP3700)
320-Gbps
Q-80G.
C192X
Q-64G
405EP
C192
160GB
q80g
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PMC-90
Abstract: PM4341A
Text: PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 3 PM4341A T1XC T1 Framer/Transceiver PM4341A T1XC DATASHEET ERRATA Issue 3: June, 1996 PMC-Sierra, Inc. 105 - 8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415 6000 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 3 PM4341A T1XC
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PM4341A
PM4341A
PMC-920902
PMC-90
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TR54016
Abstract: XRT86L38 XRT86VL34 XRT86VL34IB PIN26
Text: XRT86VL34 QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION JANUARY 2007 REV. V1.2.0 GENERAL DESCRIPTION The XRT86VL34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86VL34
XRT86VL34
TR54016
XRT86L38
XRT86VL34IB
PIN26
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m6388
Abstract: PM4314 PM4341A PM4344 PM4351 PM4388 PM6388 PM7364 PM7366 PM8313
Text: PM4388 Summary Information TOCTL OCTAL T1 FRAMER FEATURES in-band line loopback and per channel loopback code sequences. • Available in a rectangular 128 pin PQFP 14 by 20mm package. • Monolithic single chip device which integrates 8 datacom T1 framers and
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PM4388
PMC-960615R5
m6388
PM4314
PM4341A
PM4344
PM4351
PM4388
PM6388
PM7364
PM7366
PM8313
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PMC - NE 8 D
Abstract: PM4314 PM4341A PM4344 PM4351 PM4388 PM6341 PM6344 PM6388 PM7344
Text: PM8313 Summary Information D3MX M13 MULTIPLEXER / DEMULTIPLEXER FEATURES • Integrates a complete M13 multiplexer/demultiplexer in a single monolithic device. • Integral framer supports the M23 or C-bit parity DS3 formats with path maintenance data link processing
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PM8313
PMC-920522
PMC - NE 8 D
PM4314
PM4341A
PM4344
PM4351
PM4388
PM6341
PM6344
PM6388
PM7344
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n117
Abstract: No abstract text available
Text: DS3F Device DS3 Framer TXC-03401B DATA SHEET • DS3 payload access, bit-serial or nibble-parallel • C-bit parity or M13 operating mode • C-bit interface 13 C-bits in, 14 out • Detect and generate DS3 AIS, and idle signals • Transmit reference generator for serial operation
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TXC-03401B
TXC-03401B-MB
n117
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7s8gf
Abstract: 7S8G AMI SAR PM4314 PM4344 PM6341 PM6344 PM73121 PM7366 sa9g
Text: PM6344 EQUAD PMC-Sierra,Inc. Quad E1 Framer FEATURES • Monolithic single-chip device which integrates four full-featured E1 framers and transmitters for terminating duplex E1 signals. • Frames to a G.704 2.048 Mbit/s signal. Frames to the signalling multiframe
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PM6344
conditi6344
PM73121
PM4314
PMC-950510
7s8gf
7S8G
AMI SAR
PM4314
PM4344
PM6341
PM6344
PM73121
PM7366
sa9g
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ANSI T1.102
Abstract: 728A filter EASY3452 GR-499-CORE pulse shaper QUADLIU - PEB 22504
Text: P R O D U C T B R I E F DS3/STS-1/E3 Line Interface Unit The TE3-LIU former PUCCINI; PEB 3452 is a DS3 / STS-1 / E3 Line Interface Unit. It interfaces DS3 / STS-1 / E3 framer device to the analog transmission line. It fulfills the relevant standards for DS3 (44.736 Mbit/s), STS-1 (51.840 Mbit/s) and
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B119-H7614-G1-X-7600
ANSI T1.102
728A filter
EASY3452
GR-499-CORE
pulse shaper
QUADLIU - PEB 22504
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JT-G704
Abstract: PM4351
Text: PM4351 COMET Preliminary Information COMBINED T1/E1 FRAMER/TRANSCEIVER FEATURES TRANSMIT SECTION V5.1/V5.2 Interfaces • Japanese J1 Interfaces RDB R D AT R C LK I R X R ING R XTIP R V R EF R S YN C X C L K / VC L K TCL K I TD A T A [8 :0 ] WRB R LPS R e c eiv e
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PM4351
PMC-961230P2
JT-G704
PM4351
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TR62411
Abstract: DS2141A DS21Q41B DS21Q41BTN TR54016
Text: DS21Q41B Quad T1 Framer www.dalsemi.com FEATURES § § § § § § § § § § § § § § § § Four T1 DS1/ISDN-PRI framing transceivers All four framers are fully independent Frames to D4, ESF, and SLC-96 formats 8-bit parallel control port that can be
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DS21Q41B
SLC-96
DS21Q41B
128-PIN
128-PIN
56-G4011-000
TR62411
DS2141A
DS21Q41BTN
TR54016
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LR 4100 RELAY
Abstract: No abstract text available
Text: 58 AM TE-32 ASSP Telecom Standard Product Data Sheet Released r, 20 05 12 :5 3: PM4332 y, 13 De ce m be TE-32 in er In co n Tu es da High Density 32 Channel T1/E1/J1 Framer Proprietary and Confidential Released Issue No. 6: November 2005 Do wn lo ad ed by
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TE-32
PMC-2011402,
TE-32
PM4332
LR 4100 RELAY
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LR 4100 RELAY
Abstract: PM8316PGI 315-B PM8316-PGI
Text: PM8316 TEMUX 84 RELEASED DATA SHEET ISSUE 9 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX 10 :3 5: 14 PM PMC-1991437 ,1 3M ar ch ,2 00 6 PM8316 co n Mo nd ay TEMUX 84 DATA SHEET Do wn l oa de d by C on te nt T ea m of Pa rtm in er In HIGH DENSITY T1/E1 FRAMER WITH
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PMC-1991437
PM8316
PM8316
PMC-1991437
PMC-1991191
LR 4100 RELAY
PM8316PGI
315-B
PM8316-PGI
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DMO 565 R
Abstract: dmo 465 Twelve NC Code
Text: xr XRT86L34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO NOVEMBER 2004 REV. P1.1.6 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86L34
XRT86L34
DMO 565 R
dmo 465
Twelve NC Code
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RCR20
Abstract: TLHR RCR1511 RCR20 resistor CS61535A CS61574A CS61575 CS61581 CS62180A CS62180B
Text: CS62181 — Advanced Product Databook CIRRUS LOGIC FEATURES • Integrated E1 Framer for 2.048 Mbits/s Applications ■ Meets ITU-T G.704, G.706, and G.732, ETSI ETS 300-011, and ITU-T 1.431 ■ Support for CRC-4 Framing Standards and CAS/CCS Signaling Formats
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CS62181
CS62180A
CS62180B
DS2181A
CS62181
40-pin
CS62181-IL
CS62181-IQ
44-pin
RCR20
TLHR
RCR1511
RCR20 resistor
CS61535A
CS61574A
CS61575
CS61581
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Untitled
Abstract: No abstract text available
Text: IgT Integrated Telecom Technology, Inc. E3 Framer EAC-030-A User’s Manual Copyright 1994 -1 9 9 7 Integrated Telecom Technology, Inc. All Rights Reserved Integrated Telecom Technology, Inc. 18310 Montgomery Village Avenue, Suite 300 Gaithersburg, MD 20879 USA
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EAC-030-A
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