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    FEATURES OF TIGERSHARC PROCESSOR Search Results

    FEATURES OF TIGERSHARC PROCESSOR Result Highlights (6)

    Part ECAD Model Manufacturer Description Download Buy
    TMPM4GQF15FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4GRF20FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP176-2020-0.40-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4KMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4MMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4NQF10FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4NRF15FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP176-2020-0.40-002 Visit Toshiba Electronic Devices & Storage Corporation

    FEATURES OF TIGERSHARC PROCESSOR Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    ADSP-TS001

    Abstract: radix-2 TigerSHARC IMT-2000
    Text: TM ADSP-TS001 TigerSHARC DSP 1.2 Billion MACs-per-Second Static Superscalar DSP KEY FEATURES: OVERVIEW In one chip, ADI has integrated six STATIC SUPERSCALAR ARCHITECTURE OPTIMIZED FOR TELECOMMUNICATIONS INFRASTRUCTURE The ADSP-TS001 TigerSHARC DSP megabits of SRAM Synchronous


    Original     		PDF ADSP-TS001 16-bit 40-bit 32-bit 64-bit 32-bit 80-bit 128-bit radix-2 TigerSHARC IMT-2000

    8210 microprocessor

    Abstract: IMT-2000 TigerSHARC
    Text: TigerSHARC DSP TM 1.44 Billion MACs-per-Second Static Superscalar DSP KEY FEATURES: OVERVIEW In one chip, ADI has integrated six megabits STATIC SUPERSCALAR ARCHITECTURE OPTIMIZED FOR TELECOMMUNICATIONS INFRASTRUCTURE The TigerSHARC DSP targets of SRAM Static Random Access Memory ,


    Original     		PDF 64-bit 32-bit D-81373 8210 microprocessor IMT-2000 TigerSHARC

    ADSP-TS203S

    Abstract: ADSP-TS201
    Text: TigerSHARC Embedded Processor ADSP-TS203S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory


    Original     		PDF 576-ball) 32-bit 40-bit 64-bit 10-channel ADSP-TS203S BP-576 576-Ball ADSP-TS203SABP-050 ADSP-TS203S ADSP-TS201

    smd 03 jb3

    Abstract: l3bc
    Text: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory


    Original     		PDF 576-ball) 32-bit 40-bit 64-bit 14-channel ADSP-TS202S BP-576 576-Ball ADSP-TS202SABP-050 smd 03 jb3 l3bc

    ADSP-TS203S

    Abstract: ADSP-TS201
    Text: TigerSHARC Embedded Processor ADSP-TS203S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory


    Original     		PDF 576-ball) 32-bit 40-bit 64-bit 10-channel ADSP-TS203S BP-576 576-Ball ADSP-TS203SABP-050 ADSP-TS203S ADSP-TS201

    ADSP-TS203S

    Abstract: avr ms1 diagram 32x32 Multiplier EE-174 SMD-C2 32X32 MSH 11 ADSP-TS201 LXBC
    Text: PRELIMINARY TECHNICAL DATA TigerSHARC Embedded Processor ADSP-TS203S a Preliminary Technical Data KEY FEATURES 500 MHz, 2.0 ns Instruction Cycle Rate 4M Bits of Internal—On-Chip—DRAM Memory 25؋25 mm 576-Ball Thermally Enhanced Ball Grid Array Package


    Original     		PDF ADSP-TS203S 576-Ball) ADSP-TS203SABP-ENG BP-576 ADSP-TS203S avr ms1 diagram 32x32 Multiplier EE-174 SMD-C2 32X32 MSH 11 ADSP-TS201 LXBC

    ADSP-TS201

    Abstract: ADSP-TS203S AA241
    Text: TigerSHARC Embedded Processor ADSP-TS203S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory


    Original     		PDF ADSP-TS203S 576-ball) 32-bit 40-bit 64-bit 10-channel BP-576 576-Ball ADSP-TS201 ADSP-TS203S AA241

    32x32 Multiplier

    Abstract: EE-174 32X32 ADSP-TS201S processor cross reference avr ms1 diagram ADSP-TS201SABP-ENG
    Text: PRELIMINARY TECHNICAL DATA TigerSHARC Embedded Processor ADSP-TS201S a Preliminary Technical Data KEY FEATURES 500 MHz, 2.0 ns Instruction Cycle Rate 24M Bits of Internal—On-Chip—DRAM Memory 25؋25 mm 576-Ball Thermally Enhanced Ball Grid Array Package


    Original     		PDF ADSP-TS201S 576-Ball) ADSP-TS201SABP-ENG 24Mbit BP-576 32x32 Multiplier EE-174 32X32 ADSP-TS201S processor cross reference avr ms1 diagram ADSP-TS201SABP-ENG

    ADSP-TS201 SDRAM

    Abstract: TigerSHARC DSP Instruction set specification ADSP-TS201
    Text: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory


    Original     		PDF 576-ball) 32-bit 40-bit 64-bit 14-channel ADSP-TS202S BP-576 576-Ball ADSP-TS202SABP-050 ADSP-TS201 SDRAM TigerSHARC DSP Instruction set specification ADSP-TS201

    0251X

    Abstract: ADSP-TS202S smd code AA5 ADSP-TS201 SDRAM ADSP-TS201
    Text: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory


    Original     		PDF ADSP-TS202S 576-ball) 32-bit 40-bit 64-bit 14-channel ADSP-TS202SABPZ0503 BP-576 576-Ball 0251X ADSP-TS202S smd code AA5 ADSP-TS201 SDRAM ADSP-TS201

    32X32

    Abstract: ADSP-TS202S ds206 l3bc ADDR31-0 b14 smd
    Text: PRELIMINARY TECHNICAL DATA TigerSHARC Embedded Processor ADSP-TS202S a Preliminary Technical Data KEY FEATURES 500 MHz, 2.0 ns Instruction Cycle Rate 12M Bits of Internal—On-Chip—DRAM Memory 25؋25 mm 576-Ball Thermally Enhanced Ball Grid Array Package


    Original     		PDF ADSP-TS202S 576-Ball) ADSP-TS202SABP-ENG 12Mbit BP-576 32X32 ADSP-TS202S ds206 l3bc ADDR31-0 b14 smd

    Untitled

    Abstract: No abstract text available
    Text: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory


    Original     		PDF ADSP-TS202S 576-ball) 32-bit 40-bit 64-bit 14-channel ADSP-TS202SABPZ0503 BP-576 576-Ball

    BM 1084

    Abstract: ADSP-TS201Sw ADSP-TS201SWBP-050 ADSP-TS201SABP-050 ADSP-TS201SABP-060 ADSP-TS201S
    Text: TigerSHARC Embedded Processor ADSP-TS201S a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a


    Original     		PDF 576-ball) 14-channel 32-bit 40-bit 64-bit d576-Ball 576-Ball ADSP-TS201SABP-060 ADSP-TS201SABP-050 BM 1084 ADSP-TS201Sw ADSP-TS201SWBP-050 ADSP-TS201S

    ADSP-TS201SWBP-050

    Abstract: 7485 pin configuration ADSP-TS201S SYSCON 3 ADSP-TS201SABP-050 ADSP-TS201SABP-060 ADSP-TS201SwBP
    Text: TigerSHARC Embedded Processor ADSP-TS201S a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a


    Original     		PDF ADSP-TS201S 576-ball) 14-channel BP-576 D04324-0-11/04 BP-576) ADSP-TS201SWBP-050 7485 pin configuration ADSP-TS201S SYSCON 3 ADSP-TS201SABP-050 ADSP-TS201SABP-060 ADSP-TS201SwBP

    PF 08112

    Abstract: BR3100 ADSP-TS203S ADSP-TS201
    Text: TigerSHARC Embedded Processor ADSP-TS203S KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array


    Original     		PDF ADSP-TS203S 576-ball) 32-bit 40-bit 64-bit 10-channel em2012 ADSP-TS203SBBPZ050 ADSP-TS203SABP-050 PF 08112 BR3100 ADSP-TS203S ADSP-TS201

    ts201

    Abstract: ADSP-TS201S ADSP-TS201SYBP-050 PF 08112 BM 1084 ADSP-TS201 SDRAM ADSP-TS201SABP-050 ADSP-TS201SABP-060 ADSP-TS201SABPZ050 ADSP-TS201SABPZ060
    Text: TigerSHARC Embedded Processor ADSP-TS201S • a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a


    Original     		PDF ADSP-TS201S 576-ball) 14-channel 32-bit BP-576 ts201 ADSP-TS201S ADSP-TS201SYBP-050 PF 08112 BM 1084 ADSP-TS201 SDRAM ADSP-TS201SABP-050 ADSP-TS201SABP-060 ADSP-TS201SABPZ050 ADSP-TS201SABPZ060

    Untitled

    Abstract: No abstract text available
    Text: TigerSHARC Embedded Processor ADSP-TS203S KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array


    Original     		PDF ADSP-TS203S 576-ball) 32-bit 40-bit 64-bit 10-channel ADSP-TS203SBBPZ050 ADSP-TS203SABP-050 ADSP-TS203SABPZ050 BP-576

    Untitled

    Abstract: No abstract text available
    Text: TigerSHARC Embedded Processor ADSP-TS201S • a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a


    Original     		PDF ADSP-TS201S 576-ball) 14-channel 32-bit BP-576

    smd w20

    Abstract: adsp ts201 link port ts201 SMD transistor k23 y6 smd transistor 32X32 ADSP-TS202S
    Text: TigerSHARC Embedded Processor ADSP-TS202S Preliminary Technical Data KEY FEATURES KEY BENEFITS 500 MHz, 2.0 ns Instruction Cycle Rate 12M Bits of Internal—On-Chip—DRAM Memory 25x25 mm 576-Ball Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, and a Register File


    Original     		PDF ADSP-TS202S 576-Ball) High-PerforADSP-TS202SABP-X 12Mbit BP-576 C00000-0-03/03 smd w20 adsp ts201 link port ts201 SMD transistor k23 y6 smd transistor 32X32 ADSP-TS202S

    EE-68

    Abstract: ts201 Embedded Processor Preliminary Data Sheet link port ts201 32X32 ADSP-TS201S l3bc ADSP-TS201SABP-6X ADSP-TS201SABP-X
    Text: TigerSHARC Embedded Processor ADSP-TS201S Preliminary Technical Data KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns Instruction Cycle Rate 24M Bits of Internal—On-Chip—DRAM Memory 25x25 mm 576-Ball Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, a Register File, and a Communications Logic


    Original     		PDF ADSP-TS201S 576-Ball) 24Mbit BP-576 ADSP-TS201SABP-X C00000-0-03/03 BP-576) EE-68 ts201 Embedded Processor Preliminary Data Sheet link port ts201 32X32 ADSP-TS201S l3bc ADSP-TS201SABP-6X ADSP-TS201SABP-X

    ADSP-TS202S

    Abstract: ADSP-TS202
    Text: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES KEY BENEFITS 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a multiplier, a shifter, and a register file


    Original     		PDF ADSP-TS202S 576-ball) 14-channel ADSP-TS202SABP-050 BP-576 C04325-0-11/04 ADSP-TS202S ADSP-TS202

    TigerSHARC DSP Instruction set specification

    Abstract: ADSP-TS101S smd M21 ts101 dsp application note 250M 32X32 ID203
    Text: PRELIMINARY TECHNICAL DATA TigerSHARC DSP Microcomputer ADSP-TS101S a Preliminary Technical Data KEY FEATURES Operates at 250 MHz, 4.0 ns Instruction Cycle Rate Has 6M Bits of Internal—On-Chip—SRAM Memory Comes in Either a 19؋19 mm 484-Ball or 27؋27 mm


    Original     		PDF ADSP-TS101S 484-Ball) 625-Ball) ADSP-TS101SKB2250X B-625 B-484 TigerSHARC DSP Instruction set specification ADSP-TS101S smd M21 ts101 dsp application note 250M 32X32 ID203

    SMD resistors K24

    Abstract: SMD transistor k23 smd w20 ADSP-TS203S y6 smd transistor 32X32 ADSP-TS201
    Text: TigerSHARC Embedded Processor ADSP-TS203S Preliminary Technical Data KEY FEATURES KEY BENEFITS 500 MHz, 2.0 ns Instruction Cycle Rate 4M Bits of Internal—On-Chip—DRAM Memory 25x25 mm 576-Ball Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, and a Register File


    Original     		PDF ADSP-TS203S 576-Ball) ADSP-TS203SABP-X BP-576 C00000-0-03/03 SMD resistors K24 SMD transistor k23 smd w20 ADSP-TS203S y6 smd transistor 32X32 ADSP-TS201

    ADSP-TS203S

    Abstract: ADSP-TS201
    Text: TigerSHARC Embedded Processor ADSP-TS203S a KEY FEATURES KEY BENEFITS 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a multiplier, a shifter, and a register file


    Original     		PDF ADSP-TS203S 576-ball) 10-channel ADSP-TS203SABP-050 BP-576 C04326-0-11/04 ADSP-TS203S ADSP-TS201