Untitled
Abstract: No abstract text available
Text: IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS 16-BIT IDT54/74FCT162511AT/CT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: DESCRIPTION: • • • • The FCT162511T 16-bit registered/latched transceiver with parity is built
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
16-BIT
FCT162511T
MIL-STD-883,
511AT
511CT
18-Bit
|
SO56-2
Abstract: No abstract text available
Text: IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS 16-BIT IDT54/74FCT162511AT/CT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: DESCRIPTION: − − − − The FCT162511T 16-bit registered/latched transceiver with parity is
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
16-BIT
FCT162511T
MIL-STD-883,
SO56-1)
SO56-2)
SO56-3)
SO56-2
|
Untitled
Abstract: No abstract text available
Text: IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS 16-BIT IDT54/74FCT162511AT/CT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: DESCRIPTION: • • • • The FCT162511T 16-bit registered/latched transceiver with parity is built
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
250ps,
MIL-STD-883,
200pF,
FCT162511T
|
Untitled
Abstract: No abstract text available
Text: IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS 16-BIT IDT54/74FCT162511AT/CT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: DESCRIPTION: • • • • The FCT162511T 16-bit registered/latched transceiver with parity is built
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
250ps,
MIL-STD-883,
200pF,
FCT162511T
|
Untitled
Abstract: No abstract text available
Text: IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS 16-BIT IDT54/74FCT162511AT/CT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: DESCRIPTION: • • • • The FCT162511T 16-bit registered/latched transceiver with parity is built
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
16-BIT
FCT162511T
MIL-STD-883,
511AT
511CT
18-Bit
|
SO56-2
Abstract: No abstract text available
Text: IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS 16-BIT IDT54/74FCT162511AT/CT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: DESCRIPTION: − − − − The FCT162511T 16-bit registered/latched transceiver with parity is
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
16-BIT
FCT162511T
MIL-STD-883,
SO56-1)
SO56-2)
E56-1)
SO56-2
|
Untitled
Abstract: No abstract text available
Text: IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS 16-BIT IDT54/74FCT162511AT/CT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: DESCRIPTION: • • • • The FCT162511T 16-bit registered/latched transceiver with parity is built
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
250ps,
MIL-STD-883,
200pF,
FCT162511T
registereFCT162511AT/CT
|
Untitled
Abstract: No abstract text available
Text: IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS 16-BIT IDT54/74FCT162511AT/CT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: DESCRIPTION: • • • • The FCT162511T 16-bit registered/latched transceiver with parity is built
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
16-BIT
FCT162511T
MIL-STD-883,
511AT
511CT
18-Bit
|
A8-A15
Abstract: AN-121 3 bit parity checker using cmos
Text: APPLICATION NOTE AN-121 PARITY GENERATION AND CHECKING WITH THE 162511T Integrated Device Technology, Inc. By Stanley Hronik INTRODUCTION The part is packaged in IDT's 25 mil pitch SSOP and Cerpack packages and 19.6 mil pitch TSSOP packages which have multiple grounds and VCCs. The packages are designed
|
Original
|
PDF
|
AN-121
162511T
A8-A15
AN-121
3 bit parity checker using cmos
|
AN-121
Abstract: No abstract text available
Text: APPLICATION NOTE AN-121 PARITY GENERATION AND CHECKING WITH THE 162511T Integrated Device Technology, Inc. By Stanley Hronik The part is packaged in IDT's 25 mil pitch SSOP and Cerpack packages and 19.6 mil pitch TSSOP packages which have multiple grounds and VCCs. The packages are designed
|
Original
|
PDF
|
AN-121
162511T
FCT162511T
AN-121
|
SO56-2
Abstract: phase cheker
Text: Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY 0.5 MICRON CMOS Technology Typical tsk o (Output Skew) < 250ps, clocked mode Low input and output leakage ≤1µA (max)
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
250ps,
MIL-STD-883,
200pF,
FCT16.
16-BIT
SO56-1)
SO56-2
phase cheker
|
phase cheker
Abstract: B1A16 SO56-2
Text: Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • IDT54/74FCT162511AT/CT PRELIMINARY FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY 0.5 MICRON CMOS Technology Typical tsk o (Output Skew) < 250ps, clocked mode
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
250ps,
MIL-STD-883,
200pF,
FCT162511AT/CT
16-bit
phase cheker
B1A16
SO56-2
|
SO56-2
Abstract: No abstract text available
Text: IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES FAST CMOS 16-BIT IDT54/74FCT162511AT/CT REGISTERED/LATCHED TRANSCEIVER WITH PARITY DESCRIPTION: FEATURES: − − − − 0.5 MICRON CMOS Technology
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
16-BIT
250ps,
MIL-STD-883,
200pF,
SO56-1)
SO56-2)
SO56-2
|
SO56-2
Abstract: phase cheker
Text: Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY 0.5 MICRON CMOS Technology Typical tsk o (Output Skew) < 250ps, clocked mode Low input and output leakage ≤1µA (max)
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
250ps,
MIL-STD-883,
200pF,
FCT16.
16-BIT
SO56-1)
SO56-2
phase cheker
|
|
|
phase cheker
Abstract: SO56-2 fct162511ct B1A16
Text: Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • IDT54/74FCT162511AT/CT PRELIMINARY FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY 0.5 MICRON CMOS Technology Typical tsk o (Output Skew) < 250ps, clocked mode
|
Original
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
250ps,
MIL-STD-883,
200pF,
FCT162511AT/CT
16-bit
phase cheker
SO56-2
fct162511ct
B1A16
|
Untitled
Abstract: No abstract text available
Text: Integrated D evice Technology, Inc. FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • • • • • • • • 0.5 MICRON CMOS Technology Typical tsk o (Output Skew) < 250ps, clocked mode Low input and output leakage <1 ixA (max)
|
OCR Scan
|
PDF
|
16-BIT
250ps,
MIL-STD-883,
200pF,
FCT162511
16-bit
0023D44
IDT54/74FCT162511AT/CT
|
Untitled
Abstract: No abstract text available
Text: Integrated Device Technology, Inc. FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • • • • • • • • IDT54/74FCT162511AT/CT type latches and D-type flip-flops to allow data flow in transpar ent, latched or clocked modes. The device has a parity
|
OCR Scan
|
PDF
|
16-BIT
IDT54/74FCT162511AT/CT
16-BIT
MIL-STD-883,
E56-1)
162511CT
|
Untitled
Abstract: No abstract text available
Text: Integrated Device Technology, Inc. FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • • 0 .5 M IC R O N C M O S T e c h n o lo g y T yp ica l tsk o (O u tput S kew ) < 2 5 0 p s , clo cke d m o de L o w in p u t an d o u tp u t leaka ge <1 (iA (m ax)
|
OCR Scan
|
PDF
|
16-BIT
4A25771
IDT54/74FCT162511AT/CT
16-BIT
E56-1
162511CT
|
74fct162511 idt
Abstract: No abstract text available
Text: FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • • • • • • • • IDT54/74FCT162511 AT/CT PRELIMINARY type latches and D-type flip-flops to allow dataflow in transpar ent, latched or clocked modes. The device has a parity
|
OCR Scan
|
PDF
|
16-BIT
IDT54/74FCT162511
IDT54/74FCT162511AT/CT
16-BIT
MIL-STD-883,
S056-1)
S056-2'
E56-1)
162511AT
162511CT
74fct162511 idt
|
Untitled
Abstract: No abstract text available
Text: Integrated Device Technology, Inc. FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • 0.5 MICRON CM O S Technology Typical tsk o (Output Skew) < 250ps, clocked mode Low input and output leakage <1 jxA (max) ESD > 2000V per M IL-STD-883, Method 3015;
|
OCR Scan
|
PDF
|
16-BIT
250ps,
IL-STD-883,
200pF,
FCT162511AT/CT
IDT54/74FCT162511AT/CT
16-BIT
E56-1)
162511CT
|
Untitled
Abstract: No abstract text available
Text: FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY r?y integrated Devi ce Technology, Inc. FEATURES: • • • • IDT54/74FCT162511AT/CT PRELIMINARY ty p e latch es and D -typ e flip -flo p s to a llo w d a ta flo w in tra n s p a r ent, latch ed o r clo c k e d m o des. T h e d e v ic e h a s a p a rity
|
OCR Scan
|
PDF
|
16-BIT
IDT54/74FCT162511AT/CT
4A25771
16-BIT
E56-1)
162511CT
|
Untitled
Abstract: No abstract text available
Text: :9 T V FAST CM OS 1 6-BIT jjd f/ in te g ra te d D evice T e ch n o lo g y, Inc. IDT54/74FCT162511AT/CT REGISTERED/LATCHED TR A N S C E IV E R WITH PARITY FEATURES: ty p e la tc h e s a n d D -ty p e flip -flo p s to a llo w d a t a f lo w in t r a n s p a r
|
OCR Scan
|
PDF
|
IDT54/74FCT162511AT/CT
16-BIT
|
phase cheker
Abstract: psc2101
Text: H htegiated D e v iz e T e c h n o lo g y , l i e . FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • • • • • • • • 0.5 MICRON CM O S Technology Typical tsk o (Output Skew) < 250ps, clocked mode Low input and output leakage <1 jxA (max)
|
OCR Scan
|
PDF
|
16-BIT
IDT54/74FCT162511AT/CT
250ps,
IL-STD-883,
200pF,
46B5771
00E111S
48-Pin
56-Pin
phase cheker
psc2101
|
