ATV2500c
Abstract: ATF2500C programming
Text: Features • • • • • • • • • • • High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 10 ns Maximum Pin-to-pin Delay for 5V Operation Low-power Edge-sensing “L” Option with <1 mA Standby Current
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Original
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ATV2500B/BQL
ATV2500H/L
44-lead
ATF2500C
ATF2500CL
ATF2500CQ
0777F
08/01/xM
ATV2500c
ATF2500C programming
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PDF
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ATV2500c
Abstract: No abstract text available
Text: Features • • • • • • • • • • • High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 10 ns Maximum Pin-to-pin Delay for 5V Operation Low-power Edge-sensing “L” Option with <1 mA Standby Current
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Original
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ATV2500B/BQL
ATV2500H/L
44-lead
ATF2500C
ATF2500CL
ATF2500CQ
ATF2500CQL
0777E
ATV2500c
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PDF
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TEA1
Abstract: No abstract text available
Text: Features • • • • • • • • • • • High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 10 ns Maximum Pin-to-pin Delay for 5V Operation Low-power Edge-sensing “L” Option with <1 mA Standby Current
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Original
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ATV2500B/BQL
ATV2500H/L
44-lead
2500C
ATF2500C
ATF2500CL
ATF2500CQ
ATF2500CQL
0777E
TEA1
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PDF
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TTL 7400
Abstract: CY7C342 7400 datasheet ttl gate 7400 series CMOS Logic ICs 7400 series logic ICs 7400 TTL datasheet CY7C342B 7400series ttl cmos logic 7400 series
Text: This is an abbreviated datasheet. Contact a Cypress Representative for complete specifications. For new designs, please refer to the CY7C342B. 1CY 7C34 2 fax id: 6103 CY7C342 128-Macrocell MAX EPLDs Features • • • • • 128 macrocells in 8 LABs 8 dedicated inputs, 52 bidirectional I/O pins
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Original
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CY7C342B.
CY7C342
128-Macrocell
68-pin
CY7C342
7C342
TTL 7400
7400 datasheet ttl gate
7400 series CMOS Logic ICs
7400 series logic ICs
7400 TTL datasheet
CY7C342B
7400series ttl
cmos logic 7400 series
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PDF
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7400 series logic ICs
Abstract: CY7C341 CY7C341B
Text: fax id: 6105 1CY 7C34 1 This is an abbreviated data sheet. Contact a Cypress Representative for complete specifications. For new designs please refer to the CY7C341B. CY7C341 192-Macrocell MAX EPLD Features • • • • • • 92 macrocells in 12 LABs
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Original
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CY7C341B.
CY7C341
192-Macrocell
84-pin
CY7C341
7400 series logic ICs
CY7C341B
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PDF
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CY7C341B
Abstract: CY7C341
Text: fax id: 6106 1CY 7C34 1B CY7C341B 192-Macrocell MAX EPLD Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms
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Original
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CY7C341B
192-Macrocell
65-micron
84-pin
CY7C341B
CY7C341
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PDF
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1B60
Abstract: PEEL programming msi ms 1772
Text: AMI PEEL 173 SEMICONDUCTORS CM O S Programmable Electrically Erasable Logic Device February 1993 Features General Description FPLA Architecture The AMI PEEL173 is a CMOS Programmable Electrically Erasable Logic device that provides a high-performance, low-power,
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PEEL173
1B60
PEEL programming
msi ms 1772
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PDF
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Untitled
Abstract: No abstract text available
Text: fax id: 6102 CY7C343 CY7C343B 64-Macrocell MAX EPLD Functional Description Featu res • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array The CY7C343/CY7C343B is a high-performance, high-density erasable programmable logic device, available in 44-pin
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CY7C343
CY7C343B
64-Macrocell
CY7C343)
65-micron
CY7C343B)
44-pin
CY7C343/CY7C343B
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PDF
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EP610PC-35
Abstract: ep610di EP610DC-25 EP610DC-30 EP610LI EP610LC30 16 macrocell EP610PC EP610PC-30 EP610-30
Text: EP610 HIGH-PERFORMANCE 16-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3177, OCTOBER 1988—AUGUST 1989 • High-Density (Over 600 Gates) Replacement for TTL and 74HC DUAL-IN-LINE PACKAGE (TOP V IE W ) • Virtually Zero Standby Power . . . Typ 20 pA
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EP610
16-MACROCELL
D3177,
1988-AUGUST
28-PIN
EP610PC-35
ep610di
EP610DC-25
EP610DC-30
EP610LI
EP610LC30
16 macrocell
EP610PC
EP610PC-30
EP610-30
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PDF
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EP910PC-40
Abstract: EP910PC-30 EP910LC-30 bit 3501 Architecture EP910DC-40 EP910LI PACKAGE EP910DC-30 EP910 24-MACROCELL EP910DC
Text: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187, OCTOBER 1988 —REVISED AUGUST 1&89 DUA L-IN-LINE PACKAGE • High-Density (Over 900 Gates) Replacem ent for TTL and 74H C • Virtually Zero Standby P o w e r. . . Typ 20 |iA
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EP910
24-MACROCELL
D3187,
1988-BEVISED
44-PIN
EP910PC-40
EP910PC-30
EP910LC-30
bit 3501 Architecture
EP910DC-40
EP910LI PACKAGE
EP910DC-30
EP910DC
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PDF
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EP610PC-25
Abstract: EP610PC-30 16-MACROCELL EP610DC-25 EP610LI EP610PC-35 Erasable Programmable Logic Device EP610LC-30 EP610 EP610PC
Text: EP610 HIGH-PERFORMANCE 16-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3177, OCTOBER 1988-AUGUST 1989 • High-Density (Over 600 Gates) Replacement for TTL and 74HC DUAL-IN-LINE PACKAGE (TOP VIEW) • Virtually Zero Standby P ow er. . . Typ 20 pA C 1 ^ 2 4 3 vcc
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EP610
16-MACROCELL
D3177,
1988-AUGUST
28-PIN
EP610PC-25
EP610PC-30
16-MACROCELL
EP610DC-25
EP610LI
EP610PC-35
Erasable Programmable Logic Device
EP610LC-30
EP610
EP610PC
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PDF
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EP910PC-30
Abstract: EP910PC-40 EP910PC35 EP910PC-35 EP9100c EP910LC-30 EP910J EP910JC30 EP910LC-40 EP910JC-30
Text: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187. OCTOBER 1988-REVISED AUQUST 1989 DUAL-IN-LINE PAC KA G E • High-Density (Over 900 Gates) Replacement for TTL and 74HC H O P VIEW) clk C 1 V_J40 39 iC 2 • Virtually Zero Standby Power. Typ 20 nA
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EP910
24-MACROCELL
D3187.
1988-REVISED
44-PIN
EP910PC-30
EP910PC-40
EP910PC35
EP910PC-35
EP9100c
EP910LC-30
EP910J
EP910JC30
EP910LC-40
EP910JC-30
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PDF
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27C400 eprom
Abstract: 27C400 tms27c400 K1631 27PC40
Text: TMS27C400 4194 304-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC400 4 194 304-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS400A-OCTOBER 1992-REVISED JANUARY 1993 Word-Wide 256K x 16 or Byte-Wide (512K x 8) Configurable 4-Megablt Mask ROM Compatible - 40-Lead CERDIP Package
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TMS27C400
304-BIT
TMS27PC400
SMLS400A-OCTOBER
1992-REVISED
40-Lead
27C/PC400-10
27C/PC400-12
27C400 eprom
27C400
K1631
27PC40
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PDF
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27pc256
Abstract: 27e256 tms jl 27C256-15 27PC256NL TMS27C256 Bipolar PROM texas instrument 27PC256-1 TMS27C256-XXX 27c256-15 TEXAS INSTRUMENTS ti 27c256
Text: TMS27C256 2 6 2 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY S M L S 2 5 6F -S E P T E M B E R 198 4-R E V IS E D JA NUA RY 1993 This Data Sheet is Applicable to A ll TMS27C256S and TMS27PC256S Symbolized with Code “B " as Described
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OCR Scan
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TMS27C256
144-BIT
TMS27PC256
SMLS256F-SEPTEMBER
1984-REVISED
TMS27C256S
TMS27PC256S
27C/PC256-10
27C/PC256-12
27pc256
27e256
tms jl 27C256-15
27PC256NL
Bipolar PROM texas instrument
27PC256-1
TMS27C256-XXX
27c256-15 TEXAS INSTRUMENTS
ti 27c256
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PDF
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tms27pc256
Abstract: cm2 5612 TMS27C256JL S27C256 FML 612
Text: TMS27C256 262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY REVA SMLS256E - SEPTEMBER 1964 This Data Sheet is Applicable to All TMS27C256S and TMS27PC256s Symbolized with Code “B" as Described on Page 7-25.
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TMS27C256
144-BIT
TMS27PC256
SMLS256E
TMS27C256S
TMS27PC256s
TMS27C/PC256
cm2 5612
TMS27C256JL
S27C256
FML 612
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PDF
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pc 2561
Abstract: S27C256 27PC256NL
Text: TMS27C256 262.144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC256 262,144-BIT PROGRAMMABLE READ-ONLY MEMORY SEPTEMBER 1 9 8 4 -REVISED MARCH 1988 This Data Sheet is Applicable to A ll TMS27C256S a nd TMS27PC256s Sym bolized w ith Code " A " as Described on Page 12.
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OCR Scan
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TMS27C256
144-BIT
TMS27PC256
TMS27C256S
TMS27PC256s
pc 2561
S27C256
27PC256NL
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PDF
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27c291
Abstract: 27C292 27C292-5 TMS27C292 27C291-45 TMS27C291 27C291-3 27C291-50 27PC291 27C2923
Text: TMS27C291, TMS27C292 16,384-BIT UV ERASABLE PROGRAMMABLE READ ONLY MEMORIES TMS27PC291 16,384-BIT PROGRAMMABLE READ-ONLY MEMORY SEPTEMBER 1986-R EV ISED APRIL 1988 Organization . . . 2K x 8 J AND N PACKAGE TOP VIEW Single 5-V Power Supply All Inputs/Outputs TTL Compatible
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TMS27C291,
TMS27C292
384-BIT
TMS27PC291
1986-REVISED
27C/PC291-35
27C292-35
27C/PC291-45
27C292-45
27c291
27C292
27C292-5
27C291-45
TMS27C291
27C291-3
27C291-50
27PC291
27C2923
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PDF
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tms jl 27C512
Abstract: TMS27C512JE SMJ27C
Text: TMS27C512 524,288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PCS12 524,288-BIT PROGRAMMABLE READ-ONLY MEMORY 0 D 7 7 S 1 ? fl 'N O VEM B ER 1985 - REVISED APRIL 1988 J AND N PACKAGE T - t/ 6 * / 3 mZ $ ‘ TOP VIEW T ~ y é '/ 3 '¿ f A 1 5 C 1 1J 2 8 □ v c c
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TMS27C512
288-BIT
TMS27PCS12
U172S
0D77S1?
TMS27C512s
TMS27PCS12s
27C512-1
27C/PC512-2
tms jl 27C512
TMS27C512JE
SMJ27C
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PDF
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27C256-16
Abstract: tms jl 27c256-12
Text: • fllk lT SS 0 0 7 7 2 0 3 â ■ TMS27C256 262,144BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC2S6 262,144 BIT PROGRAMMABLE READ-ONLY MEMORY TEXAS INSTR ASIC/MEMORY 25E D SEPTEMBER 1964—revised march 19sb This Data Sheet is Applicable to AH
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TMS27C256
144BIT
TMS27PC2S6
TMS27C256s
TMS27PC2B6s
27C256-16
tms jl 27c256-12
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PDF
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2956
Abstract: 1065002 MN170
Text: TMS28F010A 1048576-BIT FUSH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY SM JS012-DECEM BER 1992-R E V IS E D NOVEMBER 1993 N PACKAGE O rganization. . . 128K x 8-Bit Flash Memory Pin Com patible W ith Existing 1-Megabit EPROMs V q c Tolerance ±10%
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TMS28F010A
1048576-BIT
JS012-DECEM
1992-R
28F010A-10
28F010A-12
28F010A-15
28F010A-17
168-Hour
2956
1065002
MN170
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PDF
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12950-012a
Abstract: pal 007a si 13003 al 13003 pal 005a 13003 application notes pal 003A pal 010a 13003 circuit 13003 d
Text: COM’L: H-15/25 MIL: H-20 PALCE610 Family Advanced Micro Devices EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins
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OCR Scan
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H-15/25
PALCE610
24-pln
28-pin
2950-007A
12950-012a
pal 007a
si 13003
al 13003
pal 005a
13003 application notes
pal 003A
pal 010a
13003 circuit
13003 d
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PDF
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Untitled
Abstract: No abstract text available
Text: COM’L: H-15/25 MIL: H-20 Advanced Micro Devices PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins
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OCR Scan
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H-15/25
PALCE610
24-pin
28-pin
55755b
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PDF
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Untitled
Abstract: No abstract text available
Text: COM’L: H-15/25 MIL: H-20 H Advanced Micro Devices PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins
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OCR Scan
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H-15/25
PALCE610
24-pin
28-pln
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PDF
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Untitled
Abstract: No abstract text available
Text: COM’L: H-15/25 MIL: H-20 SI PALCE610 Family Advanced Micro Devices EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins
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OCR Scan
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H-15/25
PALCE610
24-pln
28-pln
2950-007A
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PDF
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