910-A01
Abstract: No abstract text available
Text: EP910A EPLD High-Performance 24-Macrocell Device March 1993, ver. 2 Data Sheet Supplement Features □ □ P relim inary Inform ation □ □ □ □ □ □ Highest-performance 24-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns Counter frequencies up to 100 MHz
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EP910A
24-Macrocell
EP910
EP910T
EP910
24-Macrocell
910-A01
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programming manual EPLD EPS448
Abstract: Altera EPM5128 EPM7064-12 leap u1 EP-900910 PLE3-12a tcl tv circuit altera eplds EP610 "pin compatible" ALTERA MAX 5000
Text: Data Book TENTH ANNIVERSARY A Decade of Leadership A u g u s t 1993 Data Book August 1993 A-DB-0793-01 Altera, MAX, and M A X+PLUS are registered trademarks of Altera Corporation. The following, among others, are trademarks of Altera Corporation: AHDL, M AX+PLUS II, PL-ASAP2, PLDS-HPS, PLS-ADV, PLS-ES, PLS-FLEX8, PLS-FLEX8/H P, PLS-FLEX8/SN , PLS-HPS, PLS-STD, PLS-W S/H P,
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-DB-0793-01
EP330,
EP610,
EP610A,
EP610T,
EP910,
EP910A,
EP910T,
EP1810,
EP1810T,
programming manual EPLD EPS448
Altera EPM5128
EPM7064-12
leap u1
EP-900910
PLE3-12a
tcl tv circuit
altera eplds
EP610 "pin compatible"
ALTERA MAX 5000
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altera EP910
Abstract: EP910-T IEP910 altera eplds EP910EPLD
Text: t ALTERA 47E CORP D • 05*15372 00020TM - r Tfl? o - ■ c f ALT EP910 EPLDs High-Performance 24-Macrocell Devices Data Sheet September 1991, ver. 2 □ □ Features □ □ □ □ □ □ □ General Description Altera's EP910 Erasable Programmable Logic Devices EPLDs can
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00020TM
EP910
24-Macrocell
EP910T
EP910-30T
altera EP910
EP910-T
IEP910
altera eplds
EP910EPLD
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Untitled
Abstract: No abstract text available
Text: EP910A EPLD Features Preliminary Information □ □ □ □ □ □ Highest-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns - Counter frequencies up to 100 MHz - Pipelined data rates up to 125 MHz Fabricated on advanced 0.8-micron CMOS EEPROM technology
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EP910A
24-macrocell
EP910
EP910T
44-pin
EP910A1
EP910A-15
EP910A-10,
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Untitled
Abstract: No abstract text available
Text: Features tPD Altera's EP910A Erasable P rog ra m m a ble Logic D ev ice EPLD is a pincom patible version of the EP910 EPLD. It offers e nhanced p erfo rm ance and is available in 600-m il, 40-pin DIP and 44-pin J-lead chip carrier packages (see Figure 9). The E P910A E P L D contains 24 macrocells with
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EP910
EP910T
44-pin
40-pin
EP910A-25
P910A
EP910A
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altera EP910
Abstract: No abstract text available
Text: ALTERA böE CORP Features Preliminary information □ □ □ □ □ □ □ ì> GS*ìS372 □□□34D1 SÔ7 AL T Highest-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns Counter frequencies up to 100 MHz Pipelined data rates up to 125 MHz
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24-macrocell
EP910
EP910T
44-pin
EP910A1/O
EP910A
EP910A-10,
EP910A-12,
EP910A-15
altera EP910
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Untitled
Abstract: No abstract text available
Text: EP910A EPLD Features □ □ □ □ General Description Altera's EP910A Erasable Programmable Logic Device EPLD is a pincompatible version of the EP910 EPLD. It offers enhanced performance and is available in 600-mil, 40-pin DIP and 44-pin J-lead chip carrier
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EP910A
EP910
600-mil,
40-pin
44-pin
24-macrocell
EP910A-25
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