altera ep900
Abstract: EP9001
Text: D V ^ U € P 9 0 0 I cn ERASABLE P RO G R AM M AB LE L O G IC DEVICE FEATURES GENERAL DESCRIPTION • High density ¡over 900 gates? replacement for TTL and 74HC. • Advanced CHMOS EPROM technology allows erasability and reprogrammability. • High speed, tpd = 30ns.
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10/aA
EP900
altera ep900
EP9001
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altera ep900
Abstract: EP900 74HC EP910 altera EP910 ep900-2 ep9003
Text: ALTERA 24E D CO R P • 05^5375 GOOllDD r r ^ «nom s 24-M A C R O C E LL EPLO t 7 I -^ -4 7 EP900 FEATURES GENERAL DESCRIPTION • • • • • • • The Altera EP900 is a pin-compatible version of the popular EP910 Erasable Programmable Logic Device EPLD . Available in 40-pin DIP and 44-pln
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24-MACROCELL
EP900
EP910,
20/yA
0STS37E
NHt87i)
altera ep900
EP900
74HC
EP910
altera EP910
ep900-2
ep9003
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altera ep900
Abstract: altera EP910 EP900 74HC EP910 30MHx
Text: 24-M A C R O C E LL EPLD EP900 FEATURES GENERAL DESCRIPTION • High density logic replacement for TTL and 74HC. • Functional and pin compatible with the Altera EP910. • High speed, tpd = 45 ns. • Asynchronous clocking of all registers or banked register operation from 2 synchronous clocks.
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24-MACROCELL
EP910.
20/uA
MIL-STO-883
10KHI
100KM*
10MHz
30MHx
altera ep900
altera EP910
EP900
74HC
EP910
30MHx
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altera ep900
Abstract: ep900 24-MACROCELL
Text: EP900 EPLD 24-Macrocell Device June 1993, ver. 1 Data Sheet Supplement Features □ □ □ □ □ □ 24-macrocell Classic EPLD Combinatorial speeds with tPD = 50 ns Counter frequencies up to 20.0 MHz Pipelined data rates up to 23.8 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs
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EP900
24-Macrocell
EP910,
EP910A,
EP910T
00D3fcj75
altera ep900
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