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    ECL F10K Search Results

    ECL F10K Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MC1235F Rochester Electronics LLC MC1235 - Gate, ECL, CDFP14 Visit Rochester Electronics LLC Buy
    100324FM/B Rochester Electronics 100324 - TTL to ECL Translator, 6 Func, Inverted Output, ECL Visit Rochester Electronics Buy
    MC1218L Rochester Electronics LLC MC1218 - ECL to TTL Translator, ECL, CDIP14 Visit Rochester Electronics LLC Buy
    100183FC Rochester Electronics LLC Multiplier, 100K Series, 8-Bit, ECL, CQFP24, CERPAK-24 Visit Rochester Electronics LLC Buy
    MC1230F Rochester Electronics LLC XOR Gate, ECL, CDFP14 Visit Rochester Electronics LLC Buy

    ECL F10K Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    F10014

    Abstract: ECL Handbook F10506 ECL 200 F10105 f10107 F10-100 f10504
    Text: F10014 ACTIVE TERMINATOR F10K VOLTAGE COMPENSATED ECL G E N ER A L D ESC R IP TIO N — The F10014 Is a voltage com pensated ECL circuit w h ich replaces discrete diode clam ping circuits at considerable reduction in cost, board space and power dissipation. It operates from the standard - 5 . 2 V ECL


    OCR Scan     		PDF F10014 F10014 F10118 F10518 F10119 F1Q519 F10121 F10521 ECL Handbook F10506 ECL 200 F10105 f10107 F10-100 f10504

    CTR34

    Abstract: FGE2000 BL33B DFI01 Fairchild ZN 1010 L1332 JKI02 ctr-34 SHR04 OAI43
    Text: NATL SEMICOND -CMEnORY> □2E D | ts D iia b □□bi3n ? I FGE Series ECL Gate Arrays FAIRCHILD A Schlumberger Company Description FGE Series Features The FGE Series of ECL gate arrays are the fastest silicon gate arrays commercially available. These advanced ECL gate ar­


    OCR Scan     		PDF F100K 225-picosecond andRS003 TTRS103 Controller/16-out CTR34 FGE2000 BL33B DFI01 Fairchild ZN 1010 L1332 JKI02 ctr-34 SHR04 OAI43

    Fairchild ZN 1010

    Abstract: GENERAL INSTRUMENT west 2500 ic ZN 415 FGE2000
    Text: FGE Series ECL Gate Arrays PAIRCHIL.D A Schlum berc T'HO Qr>y 005596 January 1986 Description U/v\A m b The FGE Series of ECL gate arrays are the fastest silicon gate arrays com m ercially available. These advanced ECL gate arrays, ranging from 100 to 2840 equivalent gates, offer


    OCR Scan     		PDF F100K, FGE2500) 28ngton Fairchild ZN 1010 GENERAL INSTRUMENT west 2500 ic ZN 415 FGE2000

    Untitled

    Abstract: No abstract text available
    Text: F10K VOLTAGE COMPENSATED ECL SERIES GENERAL DESCRIPTION — Fairchild F10K Series Emitter Coupled Logic ECL circuitsare high speed, low power logic elements intended for use in high speed systems such as central processors, memory controllers, peripheral equipment, instrumentation and digital communication systems.


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    TR20X3

    Abstract: DFI01 OR02D
    Text: December 1989 FGA S eries A S PE C T- ECL G ate A rrays General Description The FGA Series is a new generation of ECL gate arrays based on National’s ASPECT process. These advanced ECL gate arrays, ranging from 200 to over 30,000 equiva­ lent gates, offer typical internal propagation delays of


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    FGE0500

    Abstract: FGE2000 FGE2500 F100K ECL 300 series and design guide Fairchild 100K series ECL Fairchild ZN 1010 1240 picosecond la 4440 LA 4440 circuit diagram PS-1050
    Text: FGE Series ECL Gate Arrays F A IR C H IL D A Schlumberc J/n A 005596 January 1986 n Description 0r>y ^ Gate Array Division FiC The FGE Series of ECL gate arrays are the fastest silicon gate arrays commercially available. These advanced ECL gate arrays, ranging from 100 to 2840 equivalent gates, offer


    OCR Scan     		PDF F100K 225j3 FGE0500 FGE2000 FGE2500 F100K ECL 300 series and design guide Fairchild 100K series ECL Fairchild ZN 1010 1240 picosecond la 4440 LA 4440 circuit diagram PS-1050

    AK 1230

    Abstract: No abstract text available
    Text: F10125 . F10525 QUAD ECL TO TTL TRANSLATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION — The F10125 and F10525 are Quad Translators for converting F10K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or as a differential receiver. An Internal reference voltage


    OCR Scan     		PDF F10125 F10525 F10125 F10525 AK 1230

    Untitled

    Abstract: No abstract text available
    Text: F10125 • F10525 ^ QUAD ECL TO TTL TRANSLATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION — The F10125 and F10525 are Quad Translators fo r converting F10K logic levels to TTL logic levels. D ifferential inputs allow each c irc u it to be used as an inverting, non-inverting or as a d iffe re n tia l receiver. An Internal reference voltage


    OCR Scan     		PDF F10125 F10525 F10125 F10525

    a2c33

    Abstract: No abstract text available
    Text: ECL ISOPLANAR MEMORY F10411 256x1—BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION - The F10411 is a low voltage 256-bit Read/Write Ran­ dom Access Memory, organized 256 words by one bit. It has a 20 ns typical access time


    OCR Scan     		PDF F10411 256x1--BIT F10411 256-bit 16-pin F10405, a2c33

    HA 1370 schematics

    Abstract: CMOS XNOR XOR NAND2 NAND3 ic ttl and not xor nor xnor or MICRON POWER RESISTOR 2W ECL IC NAND
    Text: PRELIMINARY Semiconductor December 1990 NGM Series ABiC BiCMOS/ECL Gate Arrays General Description Features The NGM Series is a new family of mixed ECL and BiCMOS gale arrays based on National’s revolutionary 0.8 micron drawn ABiC BiCMOS process. The NGM Series is the first


    OCR Scan     		PDF TL/U/10861-4 HA 1370 schematics CMOS XNOR XOR NAND2 NAND3 ic ttl and not xor nor xnor or MICRON POWER RESISTOR 2W ECL IC NAND

    clcc 68

    Abstract: CLCC 44 Fairchild 100K series ECL CPGA routing CLCC 24 layout CERAMIC LEADLESS CHIP CARRIER LCC 44 CERAMIC leaded CHIP CARRIER CLCC 68 CPGA132 CPGA CLCC 84
    Text: Gate Array Products FAIRCHILD A Schlum berger Com pany First/Second Q uarter 1986 Gate Array Division Fairchild Gate Array Division offers com plete in-house design and production capabilities for high perform ance ECL and CMOS gate arrays. Featured with all Fairchild ECL gate arrays are speed/power


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    eel -16-2005

    Abstract: schmitt trigger ecl F10125 F10525 Scans-0017359
    Text: / F10125 • F10525 J Q U A D ECL T O T T L T R A N S LA T O R F10K V O LT A G E C O M P E N S A T E D ECL D E SC R IPTIO N — The F10125 and F10525 are Quad Translators fo r converting F10K logic levels to TTL logic levels. D ifferential inputs allow each circu it to be used as an


    OCR Scan     		PDF F10125 F10525 F10125 F10525 eel -16-2005 schmitt trigger ecl Scans-0017359

    F10410

    Abstract: No abstract text available
    Text: ECL ISOPLANAR MEMORY F10410 256xl-BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D ESC R IPTIO N - The F10410 is a 2 5 6 -b it Read/W rite Random Access Mem­ ory, organized 256 w ords by one b it. It has ty p ic a l access tim e o f 18 ns and is designed


    OCR Scan     		PDF F10410 256xl-BIT F10410 16-pin

    F10410

    Abstract: F10410DC F10405 fairchild ECL
    Text: ECL ISOPLANAR MEMORY F10410 256xl-BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D E S C R IP T IO N The F 1 041 0 is a 2 5 6 -b it R e a d /W rite Random Access M em ory, organized 256 w ord s by one bit. It has typical access tim e of 18 ns and is


    OCR Scan     		PDF F10410 256x1-BIT F10410 256-bit 16-pin F10405, F10410DC F10405 fairchild ECL

    1117 fairchild

    Abstract: No abstract text available
    Text: ECL ISOPLANAR MEMORY F10411 256x1—BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D E S C R IP T IO N - The F10411 is a lo w voltage 2 5 6 -b it R e a d /W rite R an­ dom Access M em ory, organized 2 5 6 w ord s by one bit. It has a 2 0 ns typical access tim e


    OCR Scan     		PDF F10411 256x1--BIT F10411 1117 fairchild

    Untitled

    Abstract: No abstract text available
    Text: ECL ISOPLANAR MEMORY F10405 128x l-B IT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE C O M P E N S A T E D ECL G E N E R A L D ESC R IPTIO N - The F10405 is a 128-bit Read/W rite Random Access Mem­ ory, organized 128 w ords by one bit. It has ty p ic a l access tim e o f 12 ns and is designed


    OCR Scan     		PDF F10405 F10405 128-bit 16-pin

    si117

    Abstract: No abstract text available
    Text: F10136 • F10536 • F10137 • F10537 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10136/F10536 and F10137/F10537 are 4-stage synchronous counters capable of operating at typical count rates ot 250 MHz. The circuits are designed


    OCR Scan     		PDF F10136 F10536 F10137 F10537 F10136/F10536 F10137/F10537 F10136 modulo-16 F10137 si117

    fairchild ECL

    Abstract: F10137 F10136 F10536 F10537 ECL Handbook 125-250MHz
    Text: F10136^ F10536 • F10137 • F10537 V 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL D ESCRIPTIO N - The F10136/F10536 and F10137/F10537 are 4-stage synchronous counters capable o f operating at typical count rates of 250 MHz. The circuits are designed


    OCR Scan     		PDF F10136 F10536 F10137 F10537 F10136/F10536 F10137/F10537 F10136 modulo-16 F10137 fairchild ECL F10536 F10537 ECL Handbook 125-250MHz

    Untitled

    Abstract: No abstract text available
    Text: F10113 • F10513 ^ QUAD EXCLUSIVE OR WITH ENABLE F10K VOLTAGE COMPENSATED ECL DESCRIPTION — The F10113 and F10513 are Quad Exclusive OR Gates, with an Enable common to all four gates. When the Enable E input is HIGH, all outputs are forced LOW. LOGIC SYMBOL


    OCR Scan     		PDF F10113 F10513 F10113 F10513

    bcd counter using j-k flip flop diagram

    Abstract: pn sequence generator using jk flip flop F10136 ECL Handbook
    Text: / / / F10136 • F10536 • F10137 • F10537 V 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10136/F10536 and F10137/FI 0537 are 4-stage synchronous counters capable of operating at typical count rates of 250 MHz. The circuits are designed


    OCR Scan     		PDF F10136 F10536 F10137 F10537 F10136/F10536 F10137/FI F10136 modulo-16 F10137 bcd counter using j-k flip flop diagram pn sequence generator using jk flip flop ECL Handbook

    F10165

    Abstract: F10565
    Text: F 1 5 6 5 » F 1 1 6 5 ^ 8-INPUT PRIORITY ENCODER F10K VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION - The F10165/F10565 are 8-Input Priority Encoders with output latches. The inputs are preassigned an order of priority, with D0 having the highest priority and


    OCR Scan     		PDF F10565* F10165 F10165/F10565 F10165 F10565

    Untitled

    Abstract: No abstract text available
    Text: F10113 • F10513 QUAD EXCLUSIVE OR WITH ENABLE F10K VOLTAGE COMPENSATED ECL DESCRIPTION — The F10113 and F10513 are Quad Exclusive OR Gates, with an Enable common to all four gates. When the Enable E input is HIGH, all outputs are forced LOW. LO G IC SYMBOL


    OCR Scan     		PDF F10113 F10513 F10113 F10513

    F10145ADC

    Abstract: f10145a
    Text: FAIRCHIU3 F10145A 16x4 Register File RAM A Schtumberger Company F10K ECL Product Description The F10145A and F10545A are high-speed 64-bit Random Access Memories organized as a 16-word by 4-bit array. External logic requirements are minimized by internal address decoding, while memory expansion


    OCR Scan     		PDF F10145A F10545A 64-bit 16-word F10145A F10145ADC

    F10113

    Abstract: fairchild ECL
    Text: F10113 • F10513 QUAD EXCLUSIVE OR WITH ENABLE F10K VOLTAGE COMPENSATED ECL DESCRIPTION The F10113 and F10513 are Quad Exclusive OR Gates w ith an Enable common to all fo u r gates. When the Enable E input is HIGH, all outputs are forced LOW. LOGIC SYM BOL


    OCR Scan     		PDF F10113 F10513 F10113 F10513 vj----80 Se---20Â -Jf----20 fairchild ECL