EIA-644
Abstract: PECL-to-SN64LVDS33
Text: Interface Data Transmission Texas Instruments Incorporated The SN65LVDS33/34 as an ECL-to-LVTTL converter By Chris Sterzik Applications Specialist, Interface Products Introduction Figure 1. ECL characteristic load Emitter-coupled logic (ECL) has often been the physical
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SN65LVDS33/34
SLYT132
EIA-644
PECL-to-SN64LVDS33
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DL122
Abstract: MC10H115 MC10H116 MC10H424
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad TTL-to-ECL Translator with ECL Strobe MC10H424 The MC10H424 is a Quad TTL–to–ECL translator with an ECL strobe. Power supply requirements are ground, +5.0 volts, and –5.2 volts. L SUFFIX CERAMIC PACKAGE CASE 620–10
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MC10H424
MC10H424
MC10H424/D*
MC10H424/D
DL122
MC10H115
MC10H116
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Untitled
Abstract: No abstract text available
Text: DP8480A DP8480A 10k ECL to TTL Level Translator with Latch Literature Number: SNOSBN8A DP8480A 10k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs
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DP8480A
DP8480A
16-pin
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Untitled
Abstract: No abstract text available
Text: DP8482A DP8482A 100k ECL to TTL Level Translator with Latch Literature Number: SNOSBO0A DP8482A 100k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs
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DP8482A
DP8482A
16-pin
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Untitled
Abstract: No abstract text available
Text: 100329 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register Literature Number: SNOS122A 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register General Description The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels
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SNOS122A
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Untitled
Abstract: No abstract text available
Text: 100324 100324 Low Power Hex TTL-to-ECL Translator Literature Number: SNOS128A 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible
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SNOS128A
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F100K ECL 300 series and design guide
Abstract: F100K ECL book F100K AN-780
Text: Fairchild Semiconductor Application Note May 1991 Revised February 2004 Operating ECL from a Single Positive Supply Introduction ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the
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AN-780
F100K ECL 300 series and design guide
F100K ECL book
F100K
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DP8481
Abstract: No abstract text available
Text: DP8481 DP8481 TTL to 10k ECL Level Translator with Latch Literature Number: SNOSBN9A DP8481 TTL to 10k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with
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DP8481
DP8481
16-pin
C199/clocks
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Untitled
Abstract: No abstract text available
Text: DP8483 DP8483 TTL to 100k ECL Level Translator with Latch Literature Number: SNOSBO1A DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with
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DP8483
DP8483
16-pin
C1995
586/clocks
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F100K ECL 300 series and design guide
Abstract: ESD diode ,F100K ECL book AN-780 F100K F100K ECL book
Text: Fairchild Semiconductor Application Note May 1991 Revised May 2000 Operating ECL from a Single Positive Supply INTRODUCTION ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the
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F100K ECL 300 series and design guide
Abstract: F100K ECL book AN-780 F100K300 ,F100K ECL book F100K F100K ECL 300 series databook and design guide
Text: Fairchild Semiconductor Application Note 780 May 1991 INTRODUCTION ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the only one. Operating ECL from a positive VCC supply is a practical
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MAX7218
Abstract: 10H424
Text: MC10H424 Quad TTL to ECL Translator with ECL Strobe The MC10H424 is a Quad TTL−to−ECL translator with an ECL strobe. Power supply requirements are ground, +5.0 volts, and −5.2 volts. • Propagation Delay, 1.5 ns Typical • Improved Noise Margin 150 mV Over Operating Voltage and
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MC10H424
PLCC-20
10H424
PDIP-16
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MC10H424P
MC10H424L
50-ohm
MAX7218
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10H424
Abstract: MC10H115 MC10H116 MC10H424 MC10H424FN MC10H424L MC10H424P
Text: MC10H424 Quad TTL to ECL Translator with ECL Strobe The MC10H424 is a Quad TTL–to–ECL translator with an ECL strobe. Power supply requirements are ground, +5.0 volts, and –5.2 volts. • Propagation Delay, 1.5 ns Typical • Improved Noise Margin 150 mV Over Operating Voltage and
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MC10H424
MC10H424
MC10H424L
MC10H424P
10H424
r14525
MC10H424/D
10H424
MC10H115
MC10H116
MC10H424FN
MC10H424L
MC10H424P
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B199 RF transistor datasheet
Abstract: F100K ECL 300 series and design guide AN-780 C1995 F100K 7474-ttl AN-780 national F100K ECL book
Text: National Semiconductor Application Note 780 John Davis May 1991 INTRODUCTION ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply This is the optimum operating configuration for ECL but not the only one Operating ECL from a positive VCC supply is a
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Untitled
Abstract: No abstract text available
Text: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver
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SN65EL16
SLLS921
250-ps
MC10EL16,
MC100EL16
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T0404
Abstract: No abstract text available
Text: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver
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SLLS921
250-ps
MC10EL16,
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T0404
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SN65LVDS108
Abstract: SN65LVDS116
Text: Interface Data Transmission Texas Instruments Incorporated Power consumption of LVPECL and LVDS By Chris Sterzik Applications Specialist, Interface Products Introduction Figure 1. Models of ECL and LVDS output drivers and terminations Single-ended emitter-coupled logic (ECL) has
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SLYT127
SN65LVDS108
SN65LVDS116
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MOTOROLA ecl
Abstract: DL140 E310 LVE310 MC100E310 MC100LVE310
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage 2:8 Differential MC100LVE310 Fanout Buffer MC100E310 ECL/PECL Compatible The MC100LVE310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features
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MC100LVE310
MC100E310
MC100LVE310
LVE310
MC100E310
MC100LVE310/D*
MC100LVE310/D
DL140
MOTOROLA ecl
E310
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T0404
Abstract: T0402 capacitor MC100EL16 MC10EL16 SN65EL11 SN65EL16 SN65EL16D SN65EL16DGK
Text: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver
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SLLS921
250-ps
MC10EL16,
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T0404
T0402 capacitor
MC100EL16
MC10EL16
SN65EL11
SN65EL16
SN65EL16D
SN65EL16DGK
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Untitled
Abstract: No abstract text available
Text: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver
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SLLS921
250-ps
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Untitled
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Low Voltage 1:15 Differential MC100LVE222 ECL/PECL Clock Driver The MC100LVE222 is a low voltage, low skew 1:15 differential ECL fanout buffer designed with clock distribution in mind. The device features
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MC100LVE222
MC100LVE222
LVE222
DL140
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mc10100
Abstract: EL89
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA ECLinPS Lite Single Gate ECL Devices Features • • • • 275ps Package Gate Delays 2.0GHZ+ Flip-Flop Toggle Frequencies Space Efficient 8-Lead SOIC Package Choice of ECL Compatibility: MECL 10H™ 10EL ; or ECL
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275ps
10HTM
100EL)
100EL
mc10100
EL89
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Untitled
Abstract: No abstract text available
Text: JA! 0 2 SYNERGY SEMICONDUCTOR — Technical Specifications ECL RAMS LOW-POWER/ 10K/100K/101K ULTRA-FAST USABLE SPEED“ ERRATA November 1991 3450 Central Expressway Santa Clara, CA 95051 Tel.: 408-730-1313 Fax: 408-737-0831 ECL RAM DATA BOOK ERRATA SEMICONDUCTOR
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10K/100K/101K
SY10/100/101L484-7/8/10
10L404-7
SY10/100/101L494-7/8/10
10L494-7
O27503
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Q20P010
Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Text: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability
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Q20000
Q20000
0Q03RL
Q20P010
Q20M100
carry look ahead adder
Q20080
Q20P025
Q20025
vernier
Q20004
Q20010
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