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    DV74LS10 Search Results

    DV74LS10 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Type PDF
    DV74LS109AN AVG Semiconductors Dual J K Positive Edge Triggered Flip Flop Plastic Dip Through Hole Scan PDF
    DV74LS10N AVG Semiconductors Triple 3 Input Positive NAND Gate Plastic Dip Through Hole Scan PDF

    DV74LS10 Datasheets Context Search

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    Untitled

    Abstract: No abstract text available
    Text: AVG Semiconductors DDiT Technical Data DV74LS10 DV74ALS10A Triple 3-Input NAND Gates N Suffix Plastic DIP AVG-001 Case This device contains three independent gates, each of which performs the logic NAND function. AVG’s LS operates over extended Vcc from 4.5 to 5.5 V


    OCR Scan     		PDF DV74LS10 DV74ALS10A AVG-001 AVG-002 ALS10A DV74LS10, 1-800-AVG-SEMI

    LS109A

    Abstract: No abstract text available
    Text: AVG Semiconductors DDi Technical Data 109 A Dual JK Positive Edge-Triggered Flip-Flops DV74LS109A DV74ALS109A This device is_a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, reset and preset inputs, and also com­ plementary Q and Q outputs.


    OCR Scan     		PDF DV74LS109A DV74ALS109A DV74LS109A, 1-800-AVG-SEMI LS109A LS109A

    LS109A

    Abstract: ALS109A
    Text: A VG Semiconductors DDT Technical Data DV74LS109A DV74ALS109A This device is_a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, reset and preset inputs, and also com­ plementary Q and Q outputs. Information at input J or K is transferred to the Q output on the


    OCR Scan     		PDF DV74LS109A DV74ALS109A AVG-003 DV74LS109A, 1-800-AVG-SEMI LS109A DV74ALS109A LS109A ALS109A

    Untitled

    Abstract: No abstract text available
    Text: 107 AVG Semiconductors_ DDiT Technical Data DV74LS107A DV74ALS107 Dual JK Negative Edge-Triggered Flip-Flop N Suffix Plastic DIP AVG-001Case The 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initialized by the HIGH-toLOW transition of the clock. A LOW signal on Clear input overrides the


    OCR Scan     		PDF DV74LS107A DV74ALS107 AVG-001Case 74LS107A AVG-002 1-800-AVG-SEMI DV74LS107A, LS107A ALS107

    als10a

    Abstract: LS10 ALS-10A
    Text: AVG Semiconductors DDi TM Technical Data DV74LS10 DV74ALS10A Triple 3-Input NAND Gates N Suffix Plastic DIP AVG-001 Case This device contains three independent gates, each of which performs the logic NAND function. • • AVG’s LS operates over extended Vcc from 4.5 to 5.5 V


    OCR Scan     		PDF DV74LS10 DV74ALS10A AVG-001 AVG-002 ALS10A DV74LS10, 1-800-AVG-SEMI LS10 ALS-10A

    74ls107a

    Abstract: 74ls107 DV74ALS107
    Text: DDiT Semiconductors Technical Data DV74LS107A DV74ALS107 Dual JK Negative Edge-Triggered Flip-Flop N Suffix Plastic DIP AVG-001Case The 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initialized by the HIGH-toLOW transition of the clock. A LOW signal on Clear input overrides the


    OCR Scan     		PDF 74LS107A DV74LS107 DV74ALS107 AVG-001 AVG-002 500i2 1-800-AVG-SEMI DV74LS107A, DV74ALS107 O1011a 74ls107

    VLN 2003

    Abstract: No abstract text available
    Text: AVG Semiconductors _ppj Technical Data DV74LS10 DV74ALS10A Triple 3-Input NAND Gates N Suffix Plastic DIP A V G -001 Case This device contains three independent gates, each of which performs the logic NAND function. • •


    OCR Scan     		PDF DV74LS10 DV74ALS1 AVG-001 AVG-002 ALS10A DV74LS10, DV74ALS10A 1-800-AVG-SEMI VLN 2003