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    HM2P07PDS370N9LF Amphenol Communications Solutions Back Plane Connectors,2mm Hard Metric Series,Millipacs, Vertical Header, Type A with Peg 2.5mm, 110 Signal Pin, Press Fit Tail, 250 mating cycles and ROHS Compliant Visit Amphenol Communications Solutions
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    Switchcraft Conxall DS370

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    Advantech Co Ltd DS-370GF-U0A1E

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    DS370 Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    DS-370GB-U0A1E Advantech Embedded Computers - Single Board Computers (SBCs) - SIGNAGE CELERON J1900 2.0GHZ Original PDF
    DS-370GF-U0A1E Advantech Embedded Computers - Single Board Computers (SBCs) - SIGNAGE CELERON J1900 2.0GHZ Original PDF
    DS-370GQ-U0A1E Advantech Embedded Computers - Single Board Computers (SBCs) - SIGNAGE CELERON J1900 2.0GHZ Original PDF

    DS370 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    PDSP16256

    Abstract: PDSP16350 PDSP16510A
    Text: PDSP16256/A Programmable FIR Filter DS3709 Features ● ● ● ● ● ● ● Sixteen MACs in a Single Device Basic Mode is 16-Tap Filter at up to 25MHz Sample Rates Programmable to give up to 128 Taps with Sampling Rates Proportionally Reducing to 3•125MHz


    Original     		PDF PDSP16256/A DS3709 16-Tap 25MHz 125MHz 16-bit 32-bit PDSP16256A/C0/AC 25MHz, PDSP16256 PDSP16350 PDSP16510A

    parallel Multiplier Accumulator based on Radix-2

    Abstract: DS3707 PDSP16116 PDSP16116A PDSP16318A subtractor using TTL CMOS GG144 4 bit binary full adder and subtractor 32-bit adder block diagram for barrel shifter
    Text: PDSP16116 16 X 16 Bit Complex Multiplier Supersedes October 1996 version, DS3707 - 4.2 The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications.


    Original     		PDF PDSP16116 DS3707 PDSP16116 32-bit PDSP16116A PDSP16318A, 20MHz 20-bit parallel Multiplier Accumulator based on Radix-2 PDSP16318A subtractor using TTL CMOS GG144 4 bit binary full adder and subtractor 32-bit adder block diagram for barrel shifter

    PDSP16256

    Abstract: PDSP16350 PDSP16510A
    Text: PDSP16256/A Programmable FIR Filter DS3709 Features ● ● ● ● ● ● ● Sixteen MACs in a Single Device Basic Mode is 16-Tap Filter at up to 25MHz Sample Rates Programmable to give up to 128 Taps with Sampling Rates Proportionally Reducing to 3•125MHz


    Original     		PDF PDSP16256/A DS3709 16-Tap 25MHz 125MHz 16-bit 32-bit PDSP16256A/C0/AC 25MHz, PDSP16256 PDSP16350 PDSP16510A

    Untitled

    Abstract: No abstract text available
    Text: PDSP16256/A Programmable FIR Filter DS3709 Features ● ● ● ● ● ● ● Sixteen MACs in a Single Device Basic Mode is 16-Tap Filter at up to 25MHz Sample Rates Programmable to give up to 128 Taps with Sampling Rates Proportionally Reducing to 3•125MHz


    Original     		PDF PDSP16256/A DS3709 PDSP16256A/C0/AC 25MHz, PDSP16256 20MHz,

    FULL SUBTRACTOR using 41 MUX

    Abstract: "Overflow detection"
    Text: PDSP16318/16318A PDSP16318/PDSP16318A Complex Accumulator Advance Information Supersedes version DS3708 - 2.4 September 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and


    Original     		PDF PDSP16318/16318A PDSP16318/PDSP16318A DS3708 PDSP16318/A 20-bit 20MHz PDSP16318As PDSP16112A GC100 FULL SUBTRACTOR using 41 MUX "Overflow detection"

    4 bit barrel shifter circuit diagram

    Abstract: 4 bit barrel shifter 32 bit barrel shifter circuit diagram using mux 4 bit barrel shift register datasheet 8 bit barrel shifter 16 BIT ALU design with data sheet 32 bit barrel shifter circuit diagram barrel shifter 18 x 16 barrel shifter barrel shifter block diagram
    Text: PDSP1601/PDSP1601A PDSP1601/PDSP1601A ALU and Barrel Shifter DS3705 The PDSP1601 is a high performance 16-bit arithmetic logic unit with an independent on-chip 16-bit barrel shifter. The PDSP1601A has two operating modes giving 20MHz or 10MHz register-to-register transfer rates.


    Original     		PDF PDSP1601/PDSP1601A DS3705 PDSP1601 16-bit PDSP1601A 20MHz 10MHz 4 bit barrel shifter circuit diagram 4 bit barrel shifter 32 bit barrel shifter circuit diagram using mux 4 bit barrel shift register datasheet 8 bit barrel shifter 16 BIT ALU design with data sheet 32 bit barrel shifter circuit diagram barrel shifter 18 x 16 barrel shifter barrel shifter block diagram

    Untitled

    Abstract: No abstract text available
    Text: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS ADVANCE INFORMATION DS3708-1.1 MA544 FAMILY 10-MEMORY LD/DTMF SWITCHABLE DIALLER CHIPS The MA544 family is a range of keypad switchable LD/DTMF dialler devices with Last Number Redial facility and ten 24-digit


    Original     		PDF DS3708-1 MA544 10-MEMORY 24-digit MA545, MA547, MA541, MA548,

    8c80

    Abstract: FEN 157 PDSP16256 PDSP16350 PDSP16510A
    Text: PDSP16256/A Programmable FIR Filter DS3709 Features ● ● ● ● ● ● ● Sixteen MACs in a Single Device Basic Mode is 16-Tap Filter at up to 25MHz Sample Rates Programmable to give up to 128 Taps with Sampling Rates Proportionally Reducing to 3•125MHz


    Original     		PDF PDSP16256/A DS3709 16-Tap 25MHz 125MHz 16-bit 32-bit PDSP16256A/C0/AC 25MHz, PDSP16256 8c80 FEN 157 PDSP16350 PDSP16510A

    4 bit barrel shifter

    Abstract: barrel shifter AC84 GC100 PDSP1601 PDSP1601A PDSP16112 PDSP16116 PDSP16318 32 bit barrel shifter circuit diagram using mux
    Text: PDSP1601/PDSP1601A PDSP1601/PDSP1601A ALU and Barrel Shifter DS3705 The PDSP1601 is a high performance 16-bit arithmetic logic unit with an independent on-chip 16-bit barrel shifter. The PDSP1601A has two operating modes giving 20MHz or 10MHz register-to-register transfer rates.


    Original     		PDF PDSP1601/PDSP1601A DS3705 PDSP1601 16-bit PDSP1601A 20MHz 10MHz 4 bit barrel shifter barrel shifter AC84 GC100 PDSP16112 PDSP16116 PDSP16318 32 bit barrel shifter circuit diagram using mux

    Untitled

    Abstract: No abstract text available
    Text: PDSP16116/A OCTOBER 1996 DS3707 - 4.2 PDSP16116/A 16 BY 16 BIT COMPLEX MULTIPLIER Supersedes version October 1995 verison, DS3707 - 3.0 The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The


    Original     		PDF PDSP16116/A DS3707 PDSP16116A PDSP16116/A PDSP16318, 10MHz PDSP16116

    YR13

    Abstract: PDSP16116
    Text: PDSP16116 16 X 16 Bit Complex Multiplier DS3707 The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex 16116


    Original     		PDF PDSP16116 DS3707 PDSP16116 32-bit PDSP16116A PDSP16318A, 20MHz 20-bit YR13

    ALU of 4 bit adder and subtractor

    Abstract: circuit diagram of full subtractor circuit 16-bit adder DS3708 GC100 PDSP1601 PDSP16112 PDSP16112A PDSP16116 PDSP16330
    Text: PDSP16318/16318A PDSP16318/PDSP16318A Complex Accumulator Advance Information Supersedes version DS3708 - 2.4 September 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and


    Original     		PDF PDSP16318/16318A PDSP16318/PDSP16318A DS3708 PDSP16318/A 20-bit 20MHz PDSP16318As PDSP16112A GC100 ALU of 4 bit adder and subtractor circuit diagram of full subtractor circuit 16-bit adder GC100 PDSP1601 PDSP16112 PDSP16112A PDSP16116 PDSP16330

    FULL SUBTRACTOR using 41 MUX

    Abstract: ALU of 4 bit adder and subtractor "Overflow detection"
    Text: PDSP16318/16318A PDSP16318/PDSP16318A Advance Information Complex Accumulator Advance Information DS3708 The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz


    Original     		PDF PDSP16318/16318A PDSP16318/PDSP16318A DS3708 PDSP16318 20-bit 20MHz PDSP16318As PDSP16112A PDSP16318A/B0/AC FULL SUBTRACTOR using 41 MUX ALU of 4 bit adder and subtractor "Overflow detection"

    FULL SUBTRACTOR using 41 MUX

    Abstract: ALU of 4 bit adder and subtractor DS3708 circuit diagram of full subtractor circuit GC100 PDSP1601 PDSP16112 PDSP16112A PDSP16116 PDSP16330
    Text: PDSP16318/16318A PDSP16318/PDSP16318A Complex Accumulator Advance Information Supersedes version DS3708 - 2.4 September 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and


    Original     		PDF PDSP16318/16318A PDSP16318/PDSP16318A DS3708 PDSP16318/A 20-bit 20MHz PDSP16318As PDSP16112A GC100 FULL SUBTRACTOR using 41 MUX ALU of 4 bit adder and subtractor circuit diagram of full subtractor circuit GC100 PDSP1601 PDSP16112 PDSP16112A PDSP16116 PDSP16330

    Untitled

    Abstract: No abstract text available
    Text: W tflGEC PLESSEY P R E L IM IN A R Y IN F O R M A T IO N DS3708 - 2.0 PDSP16318/PDSP16318A COMPLEX ACCUMULATOR The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz


    OCR Scan     		PDF DS3708 PDSP16318/PDSP16318A PDSP16318 20-bit 20MHz PDSP16318As PDSP16112A 256ps. PDSP16318/13618A PDSP16318/C0/AC

    bfp 11A diode

    Abstract: No abstract text available
    Text: Si GEC PLESSEY S I M I t O N I L C T O H S P D S P 1 6 1 1 6 /A 16 BY 16 BIT COMPLEX MULTIPLIER Supersedes version October 1995 verison, DS3707 - 3.0) The PQSP16116A will multiply two complex (1 6 + 1 6 ) bit words every 50ns and can be configured to output the


    OCR Scan     		PDF DS3707 PQSP16116A PDSP16116/A PDSP16318, PDSP16116A 10MHz PDSP16116MC bfp 11A diode

    VES0010

    Abstract: No abstract text available
    Text: M IT E L PDSP16256/A Programmable FIR Filter SE M IC O N D U C T O R Supersedes version DS3709 5.1 January 1998 T h e P D S P 1 6 2 5 6 c o n ta in s s ix te e n m u ltip lie r accumulators, which can be multi cycled to provide from 16 to 128 stages of digital filtering. Input data and coefficients are


    OCR Scan     		PDF DS3709 PDSP16256/A 16-bit 16-tap 25MHz. VES0010

    Untitled

    Abstract: No abstract text available
    Text: P D S P 1601 /P D S P 1601 A MITEL ALU and Barrel Shifter SEMICONDUCTOR Supersedes version DS3705 - 2.3 September 1996 DS3705 - 3.0 The PDSP1601 is a high performance 16-bit arithmetic logic unit with an independent on-chip 16-bit barrel shifter. The PDSP1601A has two operating modes giving 20MHz or


    OCR Scan     		PDF DS3705 PDSP1601 16-bit PDSP1601A 20MHz 10MHz 16-bitfields,

    Untitled

    Abstract: No abstract text available
    Text: Si GEC P L E S S E Y OCTOBER 1997 S E M I C O N D U C T O R S DS3707 - 5.3 P D S P 16 116 16X16 BIT COMPLEX MULTIPLIER Supersedes October 1996 version, DS3707 - 4.2 The PDSP16116 contains four 1 6 x1 6 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup­


    OCR Scan     		PDF DS3707 16X16 PDSP16116 32-bit PDSP16116A PDSP16318A, 20MHz 20-bit

    FULL SUBTRACTOR using 41 MUX

    Abstract: DS3707 32 bit barrel shifter circuit diagram using multi bfp mark diode YI11 MT52L1G32D4PG-107 WT:B TR
    Text: MITEL PD SP16116 16 X 16 Bit Complex Multiplier SEMICONDUCTOR Supersedes O ctober 1996 version, DS3707 - 4.2 DS3707 - 5.3 O ctober 1997 The PDSP16116 contains four 16x16 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup­


    OCR Scan     		PDF SP16116 DS3707 PDSP16116 16x16 32-bit PDSP16116A PDSP16318A, 20MHz FULL SUBTRACTOR using 41 MUX 32 bit barrel shifter circuit diagram using multi bfp mark diode YI11 MT52L1G32D4PG-107 WT:B TR

    "Overflow detection"

    Abstract: No abstract text available
    Text: PDSP16318/PDSP16318A M ITEL Complex Accumulator SEMICONDUCTOR Supersedes version DS3708 - 2.4 Advance Inform ation Septem ber 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and


    OCR Scan     		PDF PDSP16318/PDSP16318A DS3708 PDSP16318/A 20-bit 20MHz DSP16318As PDSP16112A 16-bit "Overflow detection"

    Untitled

    Abstract: No abstract text available
    Text: GEC P L E S S E Y DS3706 • 2.4 PDSP16318/PDSP16318 A COMPLEX ACCUMULATOR Supersedes version in December 1993 D igital Video & Video D igital Signal Processing 1C Handbook, HB3923-1 The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift


    OCR Scan     		PDF DS3706 PDSP16318/PDSP16318 HB3923-1) PDSP16318 20-bit 20MHz PDSP16318As PDSP16112A PDSP16318/13618A PDSP16318A/B0/AC

    DS3707

    Abstract: No abstract text available
    Text: M ITEL PD SP16116 16 X 16 Bit Complex Multiplier SE M IC O N D U C T O R Supersedes October 1996 version, DS3707 - 4.2 DS3707 - 5.3 October 1997 The PDSP16116 contains four 1 6 x1 6 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup­


    OCR Scan     		PDF SP16116 DS3707 PDSP16116 32-bit PDSP16116A PDSP16318A, 20MHz 20-bit

    4 bit barrel shifter circuit diagram

    Abstract: 32 bit barrel shifter circuit diagram using mux 16 bit barrel shifter circuit diagram 4 bit barrel shifter circuit barrel shifter circuit diagram 4 bit barrel shifter circuit for left shift Shift register designed by Max Plus 32 bit barrel shifter circuit diagram
    Text: PDSP1601/PDSP1601A M ITEL ALU and Barrel Shifter S E M IC O N D U C T O R Supersedes version DS3705 - 2.3 September 1996 DS3705 - 3.0 November 1998 The PDSP1601 is a high performance 16-bit arithmetic logic unit with an independent on-chip 16-bit barrel shifter.


    OCR Scan     		PDF PDSP1601/PDSP1601A DS3705 PDSP1601 16-bit PDSP1601A 20MHz 10MHz 4 bit barrel shifter circuit diagram 32 bit barrel shifter circuit diagram using mux 16 bit barrel shifter circuit diagram 4 bit barrel shifter circuit barrel shifter circuit diagram 4 bit barrel shifter circuit for left shift Shift register designed by Max Plus 32 bit barrel shifter circuit diagram