IXTA32P20T
Abstract: ixth32p20t IXTQ32P20T IXTP32P20T
Text: Preliminary Technical Information IXTA32P20T IXTP32P20T IXTQ32P20T IXTH32P20T TrenchPTM Power MOSFET P-Channel Enhancement Mode Avalanche Rated TO-263 AA IXTA VDSS ID25 RDS(on) TO-220AB (IXTP) G D S G DS S D (Tab) Symbol Test Conditions VDSS TJ = 25°C to 150°C
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IXTA32P20T
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IXTQ32P20T
IXTH32P20T
O-220AB
O-247
ixth32p20t
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54AC273
Abstract: 74AC AC273 DS100288
Text: General Description Features The ’273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
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ds100288
54AC273
74AC
AC273
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74ac logic
Abstract: No abstract text available
Text: 54AC273 54AC273 Octal D Flip-Flop Literature Number: SNOS104 General Description Features The ’273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all
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54AC273
54AC273
SNOS104
74ac logic
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IXTH32P20T
Abstract: IXTA32P20T
Text: Advance Technical Information IXTA32P20T IXTP32P20T IXTH32P20T TrenchPTM Power MOSFET P-Channel Enhancement Mode Avalanche Rated VDSS ID25 = = ≤ RDS on - 200V - 32A Ω 130mΩ TO-263 AA (IXTA) G S D (Tab) TO-220AB (IXTP) Symbol Test Conditions Maximum Ratings
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IXTA32P20T
IXTP32P20T
IXTH32P20T
O-263
O-220AB
-100V
IXTA32P20T
IXTH32P20T
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Untitled
Abstract: No abstract text available
Text: Preliminary Technical Information TrenchPTM Power MOSFET P-Channel Enhancement Mode Avalanche Rated TO-263 AA IXTA VDSS ID25 IXTA32P20T IXTP32P20T IXTQ32P20T IXTH32P20T RDS(on) = = ≤ - 200V - 32A Ω 130mΩ TO-3P (IXTQ) TO-220AB (IXTP) G G D S D (Tab) G
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O-263
IXTA32P20T
IXTP32P20T
IXTQ32P20T
IXTH32P20T
O-220AB
-100V
IXTA32P20T
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Untitled
Abstract: No abstract text available
Text: + Semiconduc or 54AC273 Octal D Flip-Flop General Description Features The ’273 has e ight edge-triggered D-type flip-flops w ith indi vidual D inputs and Q o utputs. The com m on buffered C lock CP and M aster R eset (MR) input load and reset (clear) all
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54AC273
dsl00288
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