APB to I2C interface
Abstract: spi controller with apb interface AMBA AHB DMA vhdl code for ddr sdram controller with AHB interface AMBA APB spi Cypress FX2 design of dma controller using vhdl ITU656 ahb to i2c SIMPLE VGA GRAPHIC CONTROLLER
Text: LCD-Pro IP LCD-Pro IP modules DS0031 v1.01 – 20 July 2009 Datasheet: Table 1: Core Facts Implementation data Documentation Datasheet, User’s Manual Design File Formats EDIF netlist Constraint Files LPF file Reference Designs & Implementation examples
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DS0031
APB to I2C interface
spi controller with apb interface
AMBA AHB DMA
vhdl code for ddr sdram controller with AHB interface
AMBA APB spi
Cypress FX2
design of dma controller using vhdl
ITU656
ahb to i2c
SIMPLE VGA GRAPHIC CONTROLLER
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Monitran
Abstract: MH002 28UNF HP10
Text: DS0031 Issue 2 MTN/1100S Series Low profile side entry industrial accelerometer for restricted access installations Applications • Data-collector • Heavy industry • Paper machinery 26mm 2 Pin MS Connector 25mm Constant Current Source Circuit 53mm Ø10mm
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DS0031
MTN/1100S
MTN/1100SM6)
-28UNF
MTN/1100S)
MTN/MH002
Monitran
MH002
28UNF
HP10
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FPGA Virtex 6 pin configuration
Abstract: Virtex CS144 TQ144 XCV100 XCV150 XCV200 XCV300 XCV50 xapp151
Text: Virtex 2.5 V Field Programmable Gate Arrays R 3 Architectural Description The output buffer and all of the IOB control signals have independent polarity controls. VersaRing The Virtex architecture also includes the following circuits that connect to the GRM.
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DS003-1,
DS003-2,
DS003-3,
DS003-4,
DS003-2
FPGA Virtex 6 pin configuration
Virtex
CS144
TQ144
XCV100
XCV150
XCV200
XCV300
XCV50
xapp151
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tag a2
Abstract: ARGB888 CY7C68013A ITU656 RGB565 RGB888 ECP2-50 RGB-16 802.3 CRC32
Text: LCD-Pro IP user manual UM0011 v1.0 – 14 July 2009 User Manual: Overview This document describes the LCD-Pro IP architecture, including the next cores: UltiEVC display controller, UltiEBB 2D graphic accelerator, UltiEMC DDR memory controller, UltiVidin video input core, UltiDMA DMA controller, UltiSPI2AHB SPI
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UM0011
DS0031)
tag a2
ARGB888
CY7C68013A
ITU656
RGB565
RGB888
ECP2-50
RGB-16
802.3 CRC32
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XCV300
Abstract: XCV150 XCV100 XCV1000 XCV200 XCV400 XCV50 XCV600 XCV800 xcv300 pin information
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-3 v3.0 February 1, 2002 3 Product Specification Virtex Electrical Characteristics Definition of Terms Electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as Advance,
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DS003-3
DS003-1,
DS003-2,
DS003-3,
DS003-4,
XCV300
XCV150
XCV100
XCV1000
XCV200
XCV400
XCV50
XCV600
XCV800
xcv300 pin information
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NEC c317
Abstract: gm73v1892 mt 6252 Resistor Network Rpack 10K transistor NEC D 882 p CRA3A4E103J TP1017 eeprom programmer schematic 24c08 LPT22 m21cr
Text: TNETX4090 Design Manual SPWU023 October 1998 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that
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TNETX4090
SPWU023
NEC c317
gm73v1892
mt 6252
Resistor Network Rpack 10K
transistor NEC D 882 p
CRA3A4E103J
TP1017
eeprom programmer schematic 24c08
LPT22
m21cr
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Virtex
Abstract: XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50 XCV600 XCV800
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-3 v3.2 September 10, 2002 Production Product Specification Virtex Electrical Characteristics Definition of Terms Electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as Advance,
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DS003-3
DS003-1,
DS003-2,
DS003-3,
DS003-4,
Virtex
XCV100
XCV1000
XCV150
XCV200
XCV300
XCV400
XCV50
XCV600
XCV800
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Untitled
Abstract: No abstract text available
Text: DATA SHEET Z8614400ZEM 1 Z8 FAMILY ICEBOX IN-CIRCUIT INTERACTIVE REAL-TIME EMULATOR WITH FULL-FEATURED MACRO CROSS ASSEMBLER FEATURES Supported Devices: Packages Emulation 18-Pin DIP Z86144 Windows-Based User Interface RS-232 Connector
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Z8614400ZEM
18-Pin
Z86144
RS-232
Rates--9600
DS003100-Z8X0998
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Untitled
Abstract: No abstract text available
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-3 v3.1 July 19, 2002 3 Production Product Specification Virtex Electrical Characteristics Definition of Terms Electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as Advance,
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DS003-3
xapp158
DS003-1,
DS003-3,
DS003-2,
DS003-4,
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ds003
Abstract: Field Programmable Gate Arrays 512 552 XCV200 FPGA Virtex 6 pin configuration XCV1000 XCV150 XCV300 XCV400 XCV600
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-1 v2.5 April 2, 2001 3 Product Specification Features • • • • • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz
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DS003-1
66-MHz
16-bit
32-bit
16-bnd
BG560
BG256
DS003-1,
DS003-2,
DS003-3,
ds003
Field Programmable Gate Arrays
512 552
XCV200
FPGA Virtex 6 pin configuration
XCV1000
XCV150
XCV300
XCV400
XCV600
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XCV100 TQ144
Abstract: DS0034 XCV600 XCV800 ip108 DS003 AD 149 AE9 diode t25 4 L9 XCV200 TQ144
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-4 v2.7 July 19, 2001 3 Product Specification Virtex Pin Definitions Table 1: Special Purpose Pins Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 Yes Input Clock input pins that connect to Global Clock Buffers. These pins become
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DS003-4
FG676
BG352
XCV400
DS003-1,
DS003-2,
DS003-3,
DS003-4,
XCV100 TQ144
DS0034
XCV600
XCV800
ip108
DS003
AD 149 AE9
diode t25 4 L9
XCV200
TQ144
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XCV100
Abstract: XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50 XCV600 XCV800
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-3 v2.9 October 29, 2001 3 Product Specification Virtex Electrical Characteristics Definition of Terms Electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as Advance,
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DS003-3
DS003-1,
DS003-2,
DS003-3,
DS003-4,
XCV100
XCV1000
XCV150
XCV200
XCV300
XCV400
XCV50
XCV600
XCV800
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Untitled
Abstract: No abstract text available
Text: Product Obsolete/Under Obsolescence Virtex 2.5 V Field Programmable Gate Arrays R DS003-1 v4.0 March 1, 2013 Product Specification Features • • • • • Fast, high-density Field Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz
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DS003-1
66-MHz
16-bit
32-bit
XCN10016
DS003-1,
DS003-2,
DS003-3,
DS003-4,
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Untitled
Abstract: No abstract text available
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-1 v2.5 April 2, 2001 3 Product Specification Features • • • • • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz
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DS003-1
66-MHz
16-bit
32-bit
Register00
TQ144
DS003-1,
DS003-3,
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XCV100
Abstract: XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50 XCV600 XCV800 xapp151
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-1 v2.5 April 2, 2001 3 Product Specification Features • • • • • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz
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DS003-1
66-MHz
16-bit
32-bit
16-bData
FG676
BG352
XCV400
DS003-1,
XCV100
XCV1000
XCV150
XCV200
XCV300
XCV50
XCV600
XCV800
xapp151
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XCV100 TQ144
Abstract: AF3 din 74 k11 zener diode XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-1 v2.5 April 2, 2001 3 Product Specification Features • • • • • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz
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DS003-1
66-MHz
16-bit
32-bit
16-bData
FG676
BG352
XCV400
DS003-1,
XCV100 TQ144
AF3 din 74
k11 zener diode
XCV100
XCV1000
XCV150
XCV200
XCV300
XCV50
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XCV100 TQ144
Abstract: ds003 diode t25 4 L9 XCV400 XCV50 XCV600 XCV800 CS144 TQ144 DS0034
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-4 v2.8 July 19, 2002 Production Product Specification Virtex Pin Definitions Table 1: Special Purpose Pins Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 Yes Input Clock input pins that connect to Global Clock Buffers. These pins become
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DS003-4
BG352
XCV400
TQ144
DS003-1,
DS003-2,
DS003-3,
DS003-4,
XCV100 TQ144
ds003
diode t25 4 L9
XCV50
XCV600
XCV800
CS144
DS0034
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schematic diagram online UPS
Abstract: CS144 TQ144 XCV100 XCV150 XCV200 XCV300 XCV50 DS003
Text: Virtex 2.5 V Field Programmable Gate Arrays R Architectural Description The output buffer and all of the IOB control signals have independent polarity controls. VersaRing The Virtex architecture also includes the following circuits that connect to the GRM.
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DS003-1,
DS003-2,
DS003-3,
DS003-4,
DS003-2
schematic diagram online UPS
CS144
TQ144
XCV100
XCV150
XCV200
XCV300
XCV50
DS003
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FPGA Virtex 6 pin configuration
Abstract: Field Programmable Gate Arrays XCV100 TQ144 XCV400 676 package drawing 512 552 CS144 Virtex XCV100 XCV1000 XCV150
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-1 v2.5 April 2, 2001 Product Specification Features • • • • • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz - 66-MHz PCI Compliant
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DS003-1
66-MHz
16-bit
32-bit
16-bnd
BG560
BG256
DS003-1,
DS003-2,
DS003-3,
FPGA Virtex 6 pin configuration
Field Programmable Gate Arrays
XCV100 TQ144
XCV400 676 package drawing
512 552
CS144
Virtex
XCV100
XCV1000
XCV150
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D13B2
Abstract: No abstract text available
Text: Virtex 2.5 V Field Programmable Gate Arrays R 3 Architectural Description The output buffer and all of the IOB control signals have independent polarity controls. VersaRing The Virtex architecture also includes the following circuits that connect to the GRM.
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DS003-2
DS003-1,
DS003-3,
DS003-2,
DS003-4,
DS003-4
D13B2
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XCV100 TQ144
Abstract: XCV50 PQ240 B1 121 W31
Text: Virtex 2.5 V Field Programmable Gate Arrays R DS003-4 v2.5 April 2, 2001 3 Product Specification Virtex Pin Definitions Table 1: Special Purpose Pins Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 Yes Input Clock input pins that connect to Global Clock Buffers. These pins become
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DS003-4
DS003-1,
DS003-3,
DS003-2,
DS003-4,
XCV100 TQ144
XCV50 PQ240
B1 121 W31
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C8051F020
Abstract: cygnal 8051 gad4 CYGNAL c8051 development kit
Text: PRELIMINARY C8051F020/1/2/3 Mixed-Signal ISP FLASH MCU Family ANALOG PERIPHERALS - SAR ADC • 12-Bit C8051F020/1 • 10-Bit (C8051F022/3) • ± 1 LSB INL • Programmable Throughput up to 100 ksps • Up to 8 External Inputs; Programmable as Single-Ended or
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C8051F020/1/2/3
12-Bit
C8051F020/1)
10-Bit
C8051F022/3)
12-bit
CIP-51
MCS-51
DS003-1
JAN02
C8051F020
cygnal 8051
gad4
CYGNAL c8051 development kit
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FLTR100V10
Abstract: JW040A0M JW040A0M1
Text: Data Sheet July 2001 JW040A0M Power Modules; dc-dc Converters: 36 Vdc to 75 Vdc Input, 1.5 Vdc Output; 40 A; 60 W Features The JW040A0M Power Modules use advanced, surface-mount technology and deliver high-quality, efficient, and compact dc-dc conversion.
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JW040A0M
IEC60950)
73/23/EEC
93/68/EEC
DS00-319EPS
FLTR100V10
JW040A0M1
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Untitled
Abstract: No abstract text available
Text: tß Semiconductor LF442 Dual Low Pow er JF E T Input O perational A m plifier General Description Features The LF442 dual low power operational amplifiers provide many of the same AC characteristics as the industry stan dard LM1458 while greatly improving the DC characteristics
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OCR Scan
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LF442
LM1458
LM1458.
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