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    DQ15C Search Results

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    Untitled

    Abstract: No abstract text available
    Text: IBM14N1372 IBM14N3272 IBM14N6472 High Perform ance SRAM Modules Features • 256K, 512K, and 1MB secondary cache module family using Synchronous and Asynchronous SRAMs. • Organized as a 32K, 64K, or 128K x 72 package on a 4.3” x 1.1”, 160-lead, Dual Read-out DIMM


    OCR Scan     		PDF IBM14N1372 IBM14N3272 IBM14N6472 160-lead, i486/PentiumTM 50MHz 66MHz 256KB, 512KB,

    Untitled

    Abstract: No abstract text available
    Text: ADVANCE 64K x 18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, PIPELINED, BURST COUNTER AND SINGLE CYCLE DESELECT FEATURES PIN ASSIGNMENT Top View • Fast access tim e s : 4 .5 ,5 ,6 ,7 and 8ns • Fast OE access time: 5 and 6ns • • • • • • • • •


    OCR Scan     		PDF MT58LC64K18D7 160-PIN

    D4512

    Abstract: d4512844 D29D31 DQ200-V D45128
    Text: DATA SHEET MOS INTEGRATED CIRCUIT MC-4564EC726 64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE Description The M C-4564EC726 is a 67,108,864 words by 72 bits synchronous dynamic RAM module on which 36 pieces of 128 M SDRAM: ,uPD45128441 are assembled.


    OCR Scan     		PDF MC-4564EC726 72-BIT MC-4564EC726 uPD45128441 -4564EC726EFB-A80 -4564EC726EFB-A10 D4512 d4512844 D29D31 DQ200-V D45128

    BQ4025

    Abstract: bq4025Y
    Text: bq4025/bq4025Y BENCHM ARQ 256Kx16 Nonvolatile SRAM Features General Description ► D ata retention in th e absence of power The CMOS bq4025 is a nonvolatile 4,194,304-bit static RAM organized as 262,144 w ords by 16 bits. The in teg ral control circuitry an d lith ­


    OCR Scan     		PDF bq4025/bq4025Y 256Kx16 bq4025 304-bit 128Kx bq4025Y

    Untitled

    Abstract: No abstract text available
    Text: HYUNDAI H Y 6 7 V 1 6 1 1 0 /1 1 1 64K X 16 Bit SYNCHRONOUS CMOS SRAM PRELIM INARY DESCRIPTION This device integrates high-speed 64Kx16 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output All synchronous inputs pass through registers controlled by a


    OCR Scan     		PDF 64Kx16 486/Pentium 20ns/25ns/30ns 1DH03-11 MAY95 HY67V16110/111 1DH08-11-MA HY67V16110C

    Untitled

    Abstract: No abstract text available
    Text: "HYUNDAI HY67V18110/111 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst ad­ dress counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a posrtiveedge triggered clock K .


    OCR Scan     		PDF HY67V18110/111 486/Pentium 20ns/25ns/30ns 40MHz 1DH04-11-MAY95 HY67V18110/111 HY67V18110C

    Untitled

    Abstract: No abstract text available
    Text: HY UN DA I 64K X HY6718100/101 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x 18 SRAM core, address registers, data input registers, a 2-bit burst address counter and pipelined output. All synchronous inputs pass through registers controlled by a positive-edge


    OCR Scan     		PDF HY6718100/101 486/Pentium 6ns/9ns/12ns 75MHz 486/Pentlum 1DH01-22-MAY95 HY6718100/101 1DH01-22-MAY9S HY6718100C

    Untitled

    Abstract: No abstract text available
    Text: •HYUNDAI HY67V16100/101 64K X 16 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64Kx16 SRAM core, address registers, data input registers, a 2-bit burst address counter and pipelined output. All synchronous inputs pass through registers controlled by a positive-edge


    OCR Scan     		PDF HY67V16100/101 64Kx16 486/Pentium 7ns/12ns/17ns 67MHz 1DH06-11-MAY95 HY67V16100/101

    ww1 06

    Abstract: No abstract text available
    Text: TOSHIBA TENTATIVE THMY7216F0EG-80 TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY7216F0EG is a 16,777,216-word by 72-bit synchronous dynamic RAM module consisting of nine TC59SM708FT DRAMs and PLL/Registers on a printed circuit board.


    OCR Scan     		PDF THMY7216F0EG-80 THMY7216F0EG 216-word 72-bit TC59SM708FT 72-bit 168-pin ww1 06

    Untitled

    Abstract: No abstract text available
    Text: HY51V18165B Series •HYUNDAI 1M X 16-bit CMOS DRAM with Burst EDO PRELIMINARY DESCRIPTION The HY51V18165B is the new generation and fast dynamic RAM organized 1,048,576 x 16-bit. The HY51V118165B utilized Hyundai's C M O S silicon gate process technology as well as advenced circuit techniques


    OCR Scan     		PDF HY51V18165B 16-bit 16-bit. HY51V118165B 1AD63-00-MAY95 HY51V18165BJC HY51V18165BTC

    Untitled

    Abstract: No abstract text available
    Text: S G S -T H O M S O N D M a iC T G S tM O ! M 2 8 F 1 0 2 1 Megabit 64K x 16, Chip Erase FLASH MEMORY • FAST ACCESS TIME: 90ns ■ LOW POWER CONSUMPTION - Standby Current: 1OOpA Max ■ 10,000 ERASE/PROGRAM CYCLES ■ 12V PROGRAMMING VOLTAGE ■ TYPICAL BYTE PROGRAMMING TIME 10[is


    OCR Scan     		PDF PLCC44 TSOP40 PLCC44 M28F102

    DQ380-V

    Abstract: r2a11 DQ500-V
    Text: DATA SHEET MOS INTEGRATED CIRCUIT MC-4564EC727 64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE Description The M C -4 5 6 4 E C 7 2 7 is a 6 7 ,1 0 8 ,8 6 4 w o rd s by 72 bits syn ch ro n o u s d yn a m ic RAM m odule on w h ich 36 piece s of


    OCR Scan     		PDF MC-4564EC727 72-BIT MC-4564EC727 uPD45128441 DQ380-V r2a11 DQ500-V

    Untitled

    Abstract: No abstract text available
    Text: HY6718100/101 HYUNDAI 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x 18 SR A M core, address registers, data input registers, a 2-bit burst address counter and pipelined output. All synchronous inputs pass through registers controlled by a positive-edge


    OCR Scan     		PDF HY6718100/101 486/Pentium 6ns/9ns/12ns 75MHz 486/Pentium 0DDb241 1DH01-22-MAY95 HY6718100/101 4b750flfl

    Untitled

    Abstract: No abstract text available
    Text: IBM041814PQK Preliminary 6 4 K X 18 BU R ST SRAM Features • 64K x 18 Synchronous Burst Mode SRAM • 5 V Tolerant I/O • 0.5n CMOS Technology • Asynchronous Output Enable • Synchronous Burst Mode of Operation Compati­ ble with PowerPC Processors


    OCR Scan     		PDF IBM041814PQK 83MHz 50H5205 SA14-4664-00

    DQ12E

    Abstract: No abstract text available
    Text: Target CMOS DRAM KM432V504, KM432V524 512Kx32Bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a family of 524,288 x32 bit Extended Data Out CMOS DRAMs. Extended Data Out mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle


    OCR Scan     		PDF KM432V504, KM432V524 512Kx32Bit 512Kx32 DD2D35S DQ12E

    Untitled

    Abstract: No abstract text available
    Text: ADVANCE M IC R O N • MT58LC64K18F5 64Kx 18 SYNCHRONOUS SRAM SYNCHRONOUS SRAM 64Kx 18 SRAM +3.3V SUPPLY, FULLY REGISTERED INPUTS AND LATCHED OUTPUTS FEATURES • • • • • • • • • • • • Fast access times: 9 ,1 2 and 15ns Fast OE: 6 ,7 and 8ns


    OCR Scan     		PDF MT58LC64K18F5 MTS8LC64K1IF5 C1993,

    Untitled

    Abstract: No abstract text available
    Text: •HYUNDAI HY51V18165B Series 1M X 16-bit CMOS DRAM with Burst EDO PRELIMINARY DESCRIPTION The HY51V18165B is the new generation and fast dynamic RAM organized 1,048,576 x 16-bit. The HY51V118165B utilized Hyundai's CMOS silicon gate process technology as well as advenced circuit techniques


    OCR Scan     		PDF HY51V18165B 16-bit 16-bit. HY51V118165B 1AD63-00-MAY95 HY51V18165BJC HY51V18165BTC

    BA85

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM67M618A Product Preview 64K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self-Timed Write The M C M 67M 618A is a 1,179,648 bit synchronous static random access m e m ory desig n ed to provide a burstable, h ig h -p erform a n ce, se condary cache


    OCR Scan     		PDF MCM67M618A MPC604 MCM67M6 67M618A MCM67M618AFN8 MCM67M618AFN9 MCM67M618AFN10 MCM67M618AFN12 MCM67M618A BA85

    Untitled

    Abstract: No abstract text available
    Text: MICRON TECHNOLOGY INC SSE » M IC R O N • blllSMT OQG3b4T b31 H M R N MT58C1616 16K X 16 SYNCHRONOUS SRAM 16K x 16 SRAM SYNCHRONOUS SRAM WITH CLOCKED, REGISTERED INPUTS FEATURES • • • • • • • • Fast access times: 12,15,20 and 25ns Fast OE: 5,6,8 and 10ns


    OCR Scan     		PDF MT58C1616 52-Pin DQ10C DQ12C DQ14C DQ15C DQ16C

    Untitled

    Abstract: No abstract text available
    Text: Target CMOS DRAM KM432V502, KM432V522 512K x 32Bit CM O S Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 524,288 x 32 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle 1K Ref. or 4K Ref. , access time( -7 or


    OCR Scan     		PDF KM432V502, KM432V522 32Bit 512Kx32