Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    DIGITAL LOCK USING LOGIC GATES Search Results

    DIGITAL LOCK USING LOGIC GATES Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SCL3400-D01-1 Murata Manufacturing Co Ltd 2-axis (XY) digital inclinometer Visit Murata Manufacturing Co Ltd
    SCL3400-D01-004 Murata Manufacturing Co Ltd 2-axis (XY) digital inclinometer Visit Murata Manufacturing Co Ltd
    SCL3400-D01-10 Murata Manufacturing Co Ltd 2-axis (XY) digital inclinometer Visit Murata Manufacturing Co Ltd
    SCL3400-D01-PCB Murata Manufacturing Co Ltd 2-axis (XY) digital inclinometer Visit Murata Manufacturing Co Ltd
    DFE2016CKA-1R0M=P2 Murata Manufacturing Co Ltd Fixed IND 1uH 1800mA NONAUTO Visit Murata Manufacturing Co Ltd

    DIGITAL LOCK USING LOGIC GATES Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    diode BY 399 itt

    Abstract: Q20P010 M/Q20P025
    Text: DEVICE SPECIFICATION ECL/TTL “TURBO ” LOGIC ARRAYS WITH PHASE-LOCKED LOOP Q20P010/Q20P025 FEATURES On-chip high frequency phase-locked loop Up to 1.25 GHz capability Edge jitter as low as 50 ps pk-pk 900 and 3000 gates of customizable digital logic Utilizes proven Q20000* Series macro library


    OCR Scan     		Q20000* 10Ops TogP010 Q20P025 ii11n iiii111n Q20P010 Q20P025 0001b23 diode BY 399 itt M/Q20P025 PDF

    Q20P010

    Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
    Text: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability


    OCR Scan     		Q20000 Q20000 0Q03RL Q20P010 Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20004 Q20010 PDF

    verilog code of 8 bit comparator

    Abstract: full subtractor implementation using 4*1 multiplexer full subtractor circuit using decoder verilog code for multiplexer 2 to 1 verilog code for distributed arithmetic verilog code for four bit binary divider verilog code of 4 bit comparator 5 to 32 decoder using 3 to 8 decoder verilog 16 BIT ALU design with verilog code verilog code for binary division
    Text: Digital Design Using Digilent FPGA Boards - Verilog / Active-HDL Edition Table of Contents 1. Introduction to Digital Logic 1.1 Background 1.2 Digital Logic 1.3 Verilog 1 1 5 8 2. Basic Logic Gates 2.1 Truth Tables and Logic Equations The Three Basic Gates


    Original     		PDF

    vhdl code for 16 BIT BINARY DIVIDER

    Abstract: vhdl code for multiplexer 16 to 1 using 4 to 1 in vhdl code for multiplexer 32 BIT BINARY VHDL code for PWM vhdl code for motor speed control vhdl code for multiplexer 16 to 1 using 4 to 1 vhdl code for multiplexer 32 to 1 gray to binary code converter 32 BIT ALU design with vhdl code 4 bit binary multiplier Vhdl code
    Text: Digital Design Using Digilent FPGA Boards ─ VHDL / Active-HDL Edition Table of Contents 1. Introduction 1.1 Background 1.2 Digital Logic 1.3 VHDL 1 1 5 8 2. Basic Logic Gates 2.1 Truth Tables and Logic Equations The Three Basic Gates Four New Gates 2.2 Positive and Negative Logic: De Morgan’s Theorem


    Original     		PDF

    CD4046B

    Abstract: cd4046b application 3 phase inverter schematic diagram CD4018A CD4001A phase comparator PHASE COMPARATORS phase locked loop SCHA002A SCHA002
    Text: Application Report SCHA002A - February 2003 CD4046B Phase-Locked Loop: A Versatile Building Block for Micropower Digital and Analog Applications David K. Morgan Standard Linear & Logic ABSTRACT Applications of the CD4046B phase-locked loop device, such as FM demodulation, FSK


    Original     		SCHA002A CD4046B cd4046b application 3 phase inverter schematic diagram CD4018A CD4001A phase comparator PHASE COMPARATORS phase locked loop SCHA002 PDF

    pm 3132 philips vco

    Abstract: No abstract text available
    Text: Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9554-1 Data Sheet FEATURES APPLICATIONS Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and


    Original     		AD9554-1 GR-1244 GR-253 OC-192 CP-56-10) AD9554-1BCPZ AD9554-1BCPZ-REEL7 AD9554-1/PCBZ 56-Lead pm 3132 philips vco PDF

    Untitled

    Abstract: No abstract text available
    Text: CLC020 www.ti.com SNLS046E – FEBRUARY 2000 – REVISED APRIL 2013 CLC020 SMPTE 259M Digital Video Serializer with Integrated Cable Driver Check for Samples: CLC020 FEATURES DESCRIPTION • The CLC020 SMPTE 259M Digital Video Serializer with Integrated Cable Driver is a monolithic integrated


    Original     		CLC020 SNLS046E CLC020 28-Lead PDF

    Untitled

    Abstract: No abstract text available
    Text: Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9554-1 Data Sheet FEATURES APPLICATIONS Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and


    Original     		AD9554-1 GR-1244 GR-253 OC-192 CP-56-10) AD9554-1BCPZ AD9554-1BCPZ-REEL7 AD9554-1/PCBZ 56-Lead PDF

    SX-3225

    Abstract: automatic WATER LEVEL pump CONTROL disadvantage of numeric water level indicator automatic water level controller circuit diagram WATER LEVEL CONTROLLER TCXO 3225 MO-220 VMMD-4 Siward crystal xtal super-nyquist KYOCERA 50Mhz oscillator
    Text: Dual/Quad Input Network Clock Generator/Synchronizer AD9547 FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover


    Original     		AD9547 30-bit 64-Lead CP-64-4) AD9547BCPZ AD9547BCPZ-REEL7 AD9547/PCBZ CP-64-4 SX-3225 automatic WATER LEVEL pump CONTROL disadvantage of numeric water level indicator automatic water level controller circuit diagram WATER LEVEL CONTROLLER TCXO 3225 MO-220 VMMD-4 Siward crystal xtal super-nyquist KYOCERA 50Mhz oscillator PDF

    sx-3225

    Abstract: 0x0731 0x0005 GR-1244-CORE SMA100 KYOCERA 50Mhz oscillator ic master guide disadvantage of numeric water level indicator
    Text: Dual/Quad Input Network Clock Generator/Synchronizer AD9547 FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover


    Original     		AD9547 30-bit 64-Lead CP-64-4) AD9547BCPZ AD9547BCPZ-REEL71 AD9547/PCBZ1 CP-64-4 sx-3225 0x0731 0x0005 GR-1244-CORE SMA100 KYOCERA 50Mhz oscillator ic master guide disadvantage of numeric water level indicator PDF

    Untitled

    Abstract: No abstract text available
    Text: Quad/Octal Input Network Clock Generator/Synchronizer AD9548 Data Sheet FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Auto/manual holdover and reference switchover


    Original     		30-bit 10-bit MO-220-VRRD 88-Lead CP-88-2) AD9548BCPZ AD9548BCPZ-REEL7 AD9548/PCBZ PDF

    Untitled

    Abstract: No abstract text available
    Text: CLC020 www.ti.com SNLS046E – FEBRUARY 2000 – REVISED APRIL 2013 CLC020 SMPTE 259M Digital Video Serializer with Integrated Cable Driver Check for Samples: CLC020 FEATURES DESCRIPTION • The CLC020 SMPTE 259M Digital Video Serializer with Integrated Cable Driver is a monolithic integrated


    Original     		CLC020 SNLS046E CLC020 28-Lead PDF

    K1191

    Abstract: No abstract text available
    Text: Dual Input Network Clock Generator/Synchronizer AD9549 Preliminary Technical Data FEATURES APPLICATIONS Flexible Reference Inputs Input frequencies 8 kHz to 750 MHz Two reference inputs Loss of Reference indicators Auto and Manual Holdover modes Auto and Manual Switchover modes


    Original     		50MHz 64-lead 20REF MO-220-VMMD AD9549BCPZ1 AD9549XCPZ1 PR06744-0-5/07 K1191 PDF

    Untitled

    Abstract: No abstract text available
    Text: Dual/Quad Input Network Clock Generator/Synchronizer AD9547 Data Sheet FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover


    Original     		AD9547 30-bit CP-64-4) AD9547BCPZ AD9547BCPZ-REEL7 AD9547/PCBZ 64-Lead CP-64-4 PDF

    disadvantage of numeric water level indicator

    Abstract: No abstract text available
    Text: Dual/Quad Input Network Clock Generator/Synchronizer AD9547 FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover


    Original     		AD9547 30-bit 64-Lead CP-64-4) AD9547BCPZ AD9547BCPZ-REEL7 AD9547/PCBZ 091707-C disadvantage of numeric water level indicator PDF

    FEC 0642 RoHS

    Abstract: AD9584 lfcsp_VQ package 0E-18 06d6 06AC
    Text: Quad/Octal Input Network Clock Generator/Synchronizer AD9548 FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Auto/manual holdover and reference switchover


    Original     		AD9548 30-bit 30-bLead CP-88-2) AD9548BCPZ AD9548BCPZ-REEL7 AD9548/PCBZ 88-Lead CP-88-2 FEC 0642 RoHS AD9584 lfcsp_VQ package 0E-18 06d6 06AC PDF

    Untitled

    Abstract: No abstract text available
    Text: Dual/Quad Input Network Clock Generator/Synchronizer AD9547 Data Sheet FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover


    Original     		AD9547 30-bit 64-Lead CP-64-4) AD9547BCPZ AD9547BCPZ-REEL7 AD9547/PCBZ D08300-0-12/13 PDF

    disadvantage of numeric water level indicator

    Abstract: No abstract text available
    Text: Dual/Quad Input Network Clock Generator/Synchronizer AD9547 Data Sheet FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover


    Original     		30-bit 20-bit 10-bit 06-03-2013-C PKG-1184 MO-220-VMMD-4 64-Lead CP-64-4) AD9547BCPZ AD9547BCPZ-REEL7 disadvantage of numeric water level indicator PDF

    disadvantage of numeric water level indicator

    Abstract: No abstract text available
    Text: Dual/Quad Input Network Clock Generator/Synchronizer AD9547 Data Sheet FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover


    Original     		30-bit 20-bit 10-bit 06-12-2012-B MO-220-VMMD-4 64-Lead CP-64-4) AD9547BCPZ AD9547BCPZ-REEL7 AD9547/PCBZ disadvantage of numeric water level indicator PDF

    Untitled

    Abstract: No abstract text available
    Text: Dual/Quad Input Network Clock Generator/Synchronizer AD9547 Data Sheet FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover


    Original     		AD9547 30-bit CP-64-4) AD9547BCPZ AD9547BCPZ-REEL7 AD9547/PCBZ 64-Lead D08300-0-11/14 CP-64-4 PDF

    AD9549

    Abstract: SMA100 AD9549/PCBZ
    Text: Dual Input Network Clock Generator/Synchronizer AD9549 FEATURES APPLICATIONS Flexible reference inputs Input frequencies: 8 kHz to 750 MHz Two reference inputs Loss of reference indicators Auto and manual holdover modes Auto and manual switchover modes Smooth A-to-B phase transition on outputs


    Original     		AD9549 14-bit 64-Lead CP-64-7 CP-64-1 AD9549 SMA100 AD9549/PCBZ PDF

    ocxo PLL

    Abstract: FS1002 lfcsp_VQ package
    Text: Quad/Octal Input Network Clock Generator/Synchronizer AD9548 Data Sheet FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Auto/manual holdover and reference switchover


    Original     		30-bit 10-bit MO-220-VRRD 88-Lead CP-88-2) AD9548BCPZ AD9548BCPZ-REEL7 AD9548/PCBZ ocxo PLL FS1002 lfcsp_VQ package PDF

    Untitled

    Abstract: No abstract text available
    Text: Dual Input Network Clock Generator/Synchronizer AD9549 FEATURES APPLICATIONS Flexible reference inputs Input frequencies: 8 kHz to 750 MHz Two reference inputs Loss of reference indicators Auto and manual holdover modes Auto and manual switchover modes Smooth A-to-B phase transition on outputs


    Original     		AD9549 14-bit 64-Lead CP-64-7) AD9549ABCPZ AD9549ABCPZ-REEL7 AD9549A/PCBZ CP-64-7 PDF

    Untitled

    Abstract: No abstract text available
    Text: Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9554 Data Sheet FEATURES APPLICATIONS Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and


    Original     		AD9554 GR-1244 GR-253 OC-192 AD9554BCPZ AD9554BCPZ-REEL AD9554BCPZ-REEL7 AD9554/PCBZ 72-Lead PDF