40193BC
Abstract: 40192BC 74C192
Text: O ctober 1987 Revised January 1999 SEMICONDUCTOR TM D40192BC • CD40193BC Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary Counter General Description All inputs are protected against dam age due to static dis charge by clam ps to V qq and Vgs-
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CD40192BC
CD40193BC
40192BC
40193BC
D40192BC
D40193BC
74C192
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74LS
Abstract: CD40192BC CD40192BCN CD40193BC CD40193BCM CD40193BCN MM74C192 MM74C193 MS-001 N16E
Text: O ctober 1987 Revised January 1999 S E M IC O N D U C TO R T M D40192BC • CD40193BC Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary Counter General Description T he C D 40192B C and C D 40193B C up/down counters are m onolithic com plem entary MOS CMOS integrated cir
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CD40192BC
CD40193BC
CD40192BC
CD40193BC
74LS
CD40192BCN
CD40193BCM
CD40193BCN
MM74C192
MM74C193
MS-001
N16E
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74LS
Abstract: CD40192B CD40192BC CD40192BM CD40193 CD40193BC CD40193BM
Text: . & February 1988 CD40192BM/D40192BC Synchronous 4-Bit Up/Down Decade Counter CD40193BM/CD40193BC Synchronous 4-Bit Up/Down Binary Counter General Description Features These u p /d o w n co un ters are m onolithic com plem entary MOS CMOS integrated circuits. T he CD40192BM and
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CD40192BM/CD40192BC
CD40193BM/CD40193BC
CD40192BM
CD40192BC
CD40193BM
CD40193BC
74LS
CD40192B
CD40193
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D40192B
Abstract: 40193BC
Text: CD40192BM/D40192BC/CD40193BM/CD40193BC VWANational fjk Semiconductor CD40192BM/D40192BC Synchronous 4-Bit Up/Down Decade Counter CD40193BM/CD40193BC Synchronous 4-Bit Up/Down Binary Counter General Description Features These u p /d o w n counters are m onolithic com plem entary
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PDF
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CD40192BM/CD40192BC/CD40193BM/CD40193BC
CD40192BM/CD40192BC
CD40193BM/CD40193BC
D40192BM
D40192BC
40193BM
CD40193BC
D40192B
40193BC
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40192BC
Abstract: No abstract text available
Text: O ctober 1987 Revised Ja nuary 1999 S E M IC O N D U C T O R !!^ General Description All inputs are protected against dam age due to static dis charge by clam ps to V qq and Vgs- Counting up and counting down is perform ed by two count inputs, one being held HIGH w hile the oth e r is clocked. The
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CD40192BC
CD40192BC
CD40193BC
40192B
40193B
40192BC
40193BC
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74LS
Abstract: CD40192B CD40192BC CD40192BM CD40193 CD40193BC CD40193BM
Text: . & February 1988 CD40192BM/D40192BC Synchronous 4-Bit Up/Down Decade Counter CD40193BM/CD40193BC Synchronous 4-Bit Up/Down Binary Counter General Description Features These u p /d o w n co un ters are m onolithic com plem entary MOS CMOS integrated circuits. T he CD40192BM and
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OCR Scan
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PDF
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CD40192BM/CD40192BC
CD40193BM/CD40193BC
CD40192BM
CD40192BC
CD40193BM
CD40193BC
74LS
CD40192B
CD40193
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