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    CY7C1444AV33 Price and Stock

    Infineon Technologies AG CY7C1444AV33-1XWI

    IC SRAM 36MBIT PARALLEL 24FBGA
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    Infineon Technologies AG CY7C1444AV33-250AXI

    IC SRAM 36MBIT PAR 100TQFP
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    Infineon Technologies AG CY7C1444AV33-167AXC

    IC SRAM 36MBIT PAR 100TQFP
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    Infineon Technologies AG CY7C1444AV33-167AXCT

    IC SRAM 36MBIT PAR 100TQFP
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    CY7C1444AV33 Datasheets (7)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1444AV33 Cypress Semiconductor 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM Original PDF
    CY7C1444AV33-167AXC Cypress Semiconductor 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM Original PDF
    CY7C1444AV33-167AXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 167MHZ 100TQFP Original PDF
    CY7C1444AV33-167AXCT Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 167MHZ 100LQFP Original PDF
    CY7C1444AV33-167BZC Cypress Semiconductor 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM Original PDF
    CY7C1444AV33-1XWI Cypress Semiconductor 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V Original PDF
    CY7C1444AV33-250AXI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 250MHZ 100TQFP Original PDF

    CY7C1444AV33 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1444AV33 36-Mbit 1 M x 36 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Functional Description Features • Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation


    Original
    CY7C1444AV33 36-Mbit 167-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1444AV33 CY7C1445AV33 36-Mbit 1M x 36/2M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation


    Original
    CY7C1444AV33 CY7C1445AV33 36-Mbit 36/2M 250-MHz CY7C1444AV33, CY7C1445AV33 l2006-2010. PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1444AV33 CY7C1445AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz


    Original
    CY7C1444AV33 CY7C1445AV33 36-Mbit CY7C1444AV33/CY7C1445AV33 PDF

    CY7C1444AV33

    Abstract: CY7C1445AV33
    Text: CY7C1444AV33 CY7C1445AV33 36-Mbit 1M x 36/2Mx 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation


    Original
    CY7C1444AV33 CY7C1445AV33 36-Mbit 36/2Mx 250-MHz CY7C1444AV33/CY7C1445AV33 36/2M CY7C1444AV33 CY7C1445AV33 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1444AV33 36-Mbit 1 M x 36 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250 MHz and 167 MHz ■ Registered inputs and outputs for pipelined operation


    Original
    CY7C1444AV33 36-Mbit CY7C1444AV33 PDF

    CY7C1444AV33

    Abstract: CY7C1445AV33
    Text: CY7C1444AV33 CY7C1445AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz


    Original
    CY7C1444AV33 CY7C1445AV33 36-Mbit 250-MHz CY7C1444AV33 CY7C1445AV33 PDF

    CY7C1444AV33

    Abstract: CY7C1445AV33
    Text: CY7C1444AV33 CY7C1445AV33 PRELIMINARY 36-Mbit 1M x 36/2Mx 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation


    Original
    CY7C1444AV33 CY7C1445AV33 36-Mbit 36/2Mx 250-MHz CY7C1444AV33/CY7C1445AV33 100-Pin CY7C1444AV33 CY7C1445AV33 PDF

    CY7C1444AV33

    Abstract: CY7C1445AV33
    Text: CY7C1444AV33 CY7C1445AV33 36-Mbit 1M x 36/2Mx 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation


    Original
    CY7C1444AV33 CY7C1445AV33 36-Mbit 36/2Mx 250-MHz CY7C1444AV33/CY7C1445AV33 36/2M CY7C1444AV33 CY7C1445AV33 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1444AV33 36-Mbit 1 M x 36 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation


    Original
    CY7C1444AV33 36-Mbit CY7C1444AV33 PDF

    CY7C1444AV33

    Abstract: CY7C1445AV33
    Text: CY7C1444AV33 CY7C1445AV33 36-Mbit 1M x 36/2Mx 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation


    Original
    CY7C1444AV33 CY7C1445AV33 36-Mbit 36/2Mx 250-MHz CY7C1444AV33/CY7C1445AV33 36/2M CY7C1444AV33 CY7C1445AV33 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1444AV33 CY7C1445AV33 PRELIMINARY 36-Mbit 1M x 36/2Mx 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation


    Original
    CY7C1444AV33 CY7C1445AV33 36-Mbit 36/2Mx 250-MHz 200-MHz 167-MHz 100-Pin PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1444AV33 CY7C1445AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM Features Functional Description[1] • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz


    Original
    CY7C1444AV33 CY7C1445AV33 36-Mbit CY7C1444AV33/CY7C1445AV33 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1444AV33 36-Mbit 1 M x 36 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation


    Original
    CY7C1444AV33 36-Mbit CY7C1444AV33 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1444AV33 CY7C1445AV33 36-Mbit 1M x 36/2Mx 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation


    Original
    CY7C1444AV33 CY7C1445AV33 36-Mbit 36/2Mx 250-MHz 200-MHz 167-MHz PDF