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    Untitled

    Abstract: No abstract text available
    Text: CY7C14161KV18, CY7C14271KV18 CY7C14181KV18, CY7C14201KV18 36-Mbit DDR II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit Density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 333 MHz Clock for High Bandwidth ■ 2-word Burst for reducing Address Bus Frequency


    Original     		PDF CY7C14161KV18, CY7C14271KV18 CY7C14181KV18, CY7C14201KV18 36-Mbit CY7C14271KV18, CY7C14201KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C14161KV18, CY7C14271KV18 CY7C14181KV18, CY7C14201KV18 36-Mbit DDR II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit Density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 333 MHz Clock for High Bandwidth ■ 2-word Burst for reducing Address Bus Frequency


    Original     		PDF CY7C14161KV18, CY7C14271KV18 CY7C14181KV18, CY7C14201KV18 36-Mbit CY7C14271KV18, CY7C14201KV18