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CY7C1413BV18 Price and Stock

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Infineon Technologies AG CY7C1413BV18-250BZC IC SRAM 36MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1413BV18-250BZC	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Rochester Electronics LLC CY7C1413BV18-250BZC IC SRAM 36MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1413BV18-250BZC	Tray			7	1 - 10 $49.14 100 $49.14 1000 $49.14 10000 $49.14	Buy Now
Infineon Technologies AG CY7C1413BV18-200BZC IC SRAM 36MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1413BV18-200BZC	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Rochester Electronics LLC CY7C1413BV18-200BZC IC SRAM 36MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1413BV18-200BZC	Tray			7	1 - 10 $44.86 100 $44.86 1000 $44.86 10000 $44.86	Buy Now
Cypress Semiconductor CY7C1413BV18-200BZC QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165 '
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	CY7C1413BV18-200BZC		283		1	1 $43.13 10 $43.13 100 $40.54 1000 $36.66 10000 $36.66	Buy Now

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CY7C1413BV18 Datasheets (4)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1413BV18		Cypress Semiconductor	36-Mbit QDR-II SRAM 4-Word Burst Architecture		Original	PDF
CY7C1413BV18		Cypress Semiconductor	36-Mbit QDR-II SRAM 4-Word Burst Architecture		Original	PDF
CY7C1413BV18-200BZC		Cypress Semiconductor	36-Mbit QDR -II SRAM 4-Word Burst Architecture		Original	PDF
CY7C1413BV18-250BZC		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 250MHZ 165FBGA		Original	PDF

CY7C1413BV18 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
CY7C1411BV18 Abstract: CY7C1413BV18 CY7C1415BV18 CY7C1426BV18 Text: CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■	Original	CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit CY7C1411BV18 CY7C1413BV18 CY7C1411BV18 CY7C1413BV18 CY7C1415BV18 CY7C1426BV18	PDF
CY7C1411BV18 Abstract: CY7C1413BV18 CY7C1415BV18 CY7C1426BV18 Text: CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■	Original	CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit CY7C1411BV18 CY7C1413BV18 CY7C1411BV18 CY7C1413BV18 CY7C1415BV18 CY7C1426BV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1413BV18 CY7C1415BV18 36-Mbit QDR II SRAM 4-Word Burst Architecture 36-Mbit QDR® II SRAM 4-Word Burst Architecture Features • JTAG 1149.1 compatible test access port ■ Delay Lock Loop DLL for accurate data placement ■ Separate independent read and write data ports	Original	CY7C1413BV18 CY7C1415BV18 36-Mbit	PDF
Untitled Abstract: No abstract text available Text: CY7C1413BV18 CY7C1415BV18 36-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1413BV18 – 2M x 18 ■ 300 MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency	Original	CY7C1413BV18 CY7C1415BV18 36-Mbit CY7C1413BV18	PDF
CY7C1411BV18 Abstract: CY7C1413BV18 CY7C1415BV18 CY7C1426BV18 Text: CY7C1411BV18 CY7C1426BV18 CY7C1413BV18 CY7C1415BV18 PRELIMINARY 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth	Original	CY7C1411BV18 CY7C1426BV18 CY7C1413BV18 CY7C1415BV18 36-Mbit 300-MHz CY7C1411BV18 CY7C1413BV18 CY7C1415BV18 CY7C1426BV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1413BV18 CY7C1415BV18 36-Mbit QDR II SRAM 4-Word Burst Architecture 36-Mbit QDR® II SRAM 4-Word Burst Architecture Features • JTAG 1149.1 compatible test access port ■ Delay Lock Loop DLL for accurate data placement ■ Separate independent read and write data ports	Original	CY7C1413BV18 CY7C1415BV18 36-Mbit	PDF