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3M Touch Systems Abstract: No abstract text available Text: CY7C1241KV18, CY7C1256KV18 CY7C1243KV18, CY7C1245KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports	Original	PDF	36-Mbit CY7C1241KV18, CY7C1256KV18 CY7C1243KV18, CY7C1245KV18 CY7C1241KV18 CY7C1256KV18 CY7C1243KV18 3M Touch Systems
CY7C1245KV18-400BZXI Abstract: 3M Touch Systems Text: CY7C1241KV18, CY7C1256KV18 CY7C1243KV18, CY7C1245KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports	Original	PDF	36-Mbit CY7C1241KV18, CY7C1256KV18 CY7C1243KV18, CY7C1245KV18 CY7C1241KV18 CY7C1256KV18 CY7C1243KV18 CY7C1245KV18-400BZXI 3M Touch Systems
3M Touch Systems Abstract: No abstract text available Text: CY7C1241KV18, CY7C1256KV18 CY7C1243KV18, CY7C1245KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports	Original	PDF	36-Mbit CY7C1241KV18, CY7C1256KV18 CY7C1243KV18, CY7C1245KV18 CY7C1241KV18 CY7C1256KV18 CY7C1243KV18 3M Touch Systems
Untitled Abstract: No abstract text available Text: CY7C1243KV18/CY7C1245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions	Original	PDF	CY7C1243KV18/CY7C1245KV18 36-Mbit CY7C1245KV18
Untitled Abstract: No abstract text available Text: CY7C1243KV18, CY7C1245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Configurations Features Separate independent read and write data ports ❐ Supports concurrent transactions	Original	PDF	CY7C1243KV18, CY7C1245KV18 36-Mbit
3M Touch Systems Abstract: No abstract text available Text: CY7C1243KV18, CY7C1245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions	Original	PDF	CY7C1243KV18, CY7C1245KV18 36-Mbit CY7C1243KV18 3M Touch Systems