CY7C1243V18 Search Results

CY7C1243V18 Datasheets (3)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1243V18		Cypress Semiconductor	36-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)		Original	PDF
CY7C1243V18-333BZC		Cypress Semiconductor	36-Mbit QDR -II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)		Original	PDF
CY7C1243V18-333BZXC		Cypress Semiconductor	36-Mbit QDR -II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: QDR-II+, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V		Original	PDF

CY7C1243V18 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
FBGA-15 Abstract: No abstract text available Text: CY7C1243V18 CY7C1245V18 PRELIMINARY 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 375 MHz clock for high bandwidth	Original	PDF	CY7C1243V18 CY7C1245V18 36-Mbit FBGA-15
Untitled Abstract: No abstract text available Text: CY7C1256V18 CY7C1243V18 CY7C1245V18 PRELIMINARY 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • Separate Independent Read and Write data ports With Read Cycle Latency of 2.0 cycles: — Supports concurrent transactions	Original	PDF	CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit CY7C1256V18/CY7C1243V18/CY7C1245V18 CY7C1256AV18
CY7C1241V18 Abstract: CY7C1243V18 CY7C1245V18 CY7C1256V18 Text: CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs,	Original	PDF	CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit CY7C1241V18, CY7C1256V18, CY7C1243V18, CY7C1245V18 CY7C1241V18 CY7C1243V18 CY7C1256V18
Untitled Abstract: No abstract text available Text: CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs,	Original	PDF	CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit
CY7C1241V18 Abstract: CY7C1243V18 CY7C1245V18 CY7C1256V18 Text: CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles:	Original	PDF	CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 36-Mbit CY7C1241V18 CY7C1243V18 CY7C1245V18 CY7C1256V18
Untitled Abstract: No abstract text available Text: CY7C1276V18 CY7C1263V18 CY7C1265V18 PRELIMINARY 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit CY7C1276V18/CY7C1263V18/CY7C1265V18 CY7C1256AV18