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    CY7C1241V18 Search Results

    CY7C1241V18 Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1241V18 Cypress Semiconductor 36-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Original PDF

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    CY7C1241V18

    Abstract: CY7C1243V18 CY7C1245V18 CY7C1256V18
    Text: CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs,


    Original     		PDF CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit CY7C1241V18, CY7C1256V18, CY7C1243V18, CY7C1245V18 CY7C1241V18 CY7C1243V18 CY7C1256V18

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    Abstract: No abstract text available
    Text: CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs,


    Original     		PDF CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit

    CY7C1241V18

    Abstract: CY7C1243V18 CY7C1245V18 CY7C1256V18
    Text: CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles:


    Original     		PDF CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 36-Mbit CY7C1241V18 CY7C1243V18 CY7C1245V18 CY7C1256V18