3M Touch Systems
Abstract: No abstract text available
Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
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Original
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CY7C11461KV18,
CY7C11571KV18
CY7C11481KV18,
CY7C11501KV18
18-Mbit
CY7C11571KV18,
CY7C11501KV18
3M Touch Systems
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PDF
|
Untitled
Abstract: No abstract text available
Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth
|
Original
|
CY7C11461KV18,
CY7C11571KV18
CY7C11481KV18,
CY7C11501KV18
18-Mbit
CY7C11571KV18,
CY7C11501KV18
CY7C11461KV18)
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth
|
Original
|
CY7C11461KV18,
CY7C11571KV18
CY7C11481KV18,
CY7C11501KV18
18-Mbit
CY7C11571KV18,
CY7C11501KV18
CY7C11461KV18)
|
PDF
|
3M Touch Systems
Abstract: No abstract text available
Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth
|
Original
|
CY7C11461KV18,
CY7C11571KV18
CY7C11481KV18,
CY7C11501KV18
18-Mbit
3M Touch Systems
|
PDF
|