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    CY7C11501KV18 Search Results

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    CY7C11501KV18 Price and Stock

    Rochester Electronics LLC CY7C11501KV18-400BZXI

    IC SRAM 18MBIT PARALLEL 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C11501KV18-400BZXI Tray 655 7
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    Infineon Technologies AG CY7C11501KV18-400BZXC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C11501KV18-400BZXC Tray
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    Rochester Electronics LLC CY7C11501KV18-400BZXC

    IC SRAM 18MBIT PARALLEL 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C11501KV18-400BZXC Tray 7
    • 1 -
    • 10 $43.7
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    Infineon Technologies AG CY7C11501KV18-400BZXI

    IC SRAM 18MBIT PARALLEL 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C11501KV18-400BZXI Tray
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    Cypress Semiconductor CY7C11501KV18-400BZXC

    CY7C11501KV18 - DDR SRAM, 512KX36, 0.45ns PBGA165 '
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    Rochester Electronics CY7C11501KV18-400BZXC 1,473 1
    • 1 $44.12
    • 10 $44.12
    • 100 $41.47
    • 1000 $37.5
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    CY7C11501KV18 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Type PDF
    CY7C11501KV18-400BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 400MHZ 165FBGA Original PDF
    CY7C11501KV18-400BZXI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 400MHZ 165FBGA Original PDF

    CY7C11501KV18 Datasheets Context Search

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    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36)


    Original
    PDF CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit CY7C11571KV18, CY7C11501KV18 3M Touch Systems

    Untitled

    Abstract: No abstract text available
    Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth


    Original
    PDF CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit CY7C11571KV18, CY7C11501KV18 CY7C11461KV18)

    Untitled

    Abstract: No abstract text available
    Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth


    Original
    PDF CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit CY7C11571KV18, CY7C11501KV18 CY7C11461KV18)

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth


    Original
    PDF CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit 3M Touch Systems