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    QS5991

    Abstract: CY7B991 CY7B992 QS5992 QS5993
    Text: QS5991, QS5992, QS5993 QS5991 QS5992 QS5993 Programmable Skew PLL Clock Driver TurboClock Q QUALITY SEMICONDUCTOR, INC. FEATURES/BENEFITS DESCRIPTION • • • The QS599X family is a high fanout PLL based clock driver intended for high performance computing and


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    PDF QS5991, QS5992, QS5993 QS5991 QS5992 QS599X QS5991 QS5993 CY7B991 CY7B992 QS5992

    CY7B9910

    Abstract: CY7B9920
    Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines


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    PDF CY7B9910 CY7B9920 80-MHz 24-pin CY7B9910 CY7B9920

    CY7B9910

    Abstract: CY7B9920
    Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows


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    PDF CY7B9910 CY7B9920 24-pin CY7B9910 CY7B9920

    CY7B991

    Abstract: No abstract text available
    Text: CY7B991 CY7B992 Programmable Skew Clock Buffer Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 ps maximum ■ 3.75 MHz to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns


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    PDF CY7B991 CY7B992 CY7B992

    Untitled

    Abstract: No abstract text available
    Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows


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    PDF CY7B9910 CY7B9920 24-pin

    Untitled

    Abstract: No abstract text available
    Text: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 maximum ■ 3.75 to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns ❐ Inverted and non-inverted


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    PDF CY7B991 CY7B992 CY7B992

    Untitled

    Abstract: No abstract text available
    Text: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 maximum ■ 3.75 to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns ❐ Inverted and non-inverted


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    PDF CY7B991 CY7B992 CY7B992

    Untitled

    Abstract: No abstract text available
    Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs


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    PDF CY7B9910 CY7B9920 24-pin

    CY7B9910

    Abstract: CY7B9920
    Text: CY7B9910 CY7B9920 W ances as low as 50 while delivering miniĆ mal and specified output skews and fullĆ swing logic levels CY7B9910 TTL or CY7B9920 CMOS . Features D All outputs skew <100 ps typical (250 max.) D D D D D D D 15Ć to 80ĆMHz output operation


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    PDF CY7B9910 CY7B9920 CY7B9910 CY7B9920 80MHz

    CY7B991-7JI

    Abstract: CY7B991 7B991 CY7B992 CY7B991-7LMB
    Text: 92 CY7B991 CY7B992 Programmable Skew Clock Buffer Features functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can


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    PDF CY7B991 CY7B992 CY7B991 CY7B992 80-MHz CY7B991/CY7B992 CY7B991-7JI 7B991 CY7B991-7LMB

    CY7B9910

    Abstract: CY7B9920 BUT12
    Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs


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    PDF CY7B9910 CY7B9920 24-pin CY7B9910 CY7B9920 BUT12

    Untitled

    Abstract: No abstract text available
    Text: CY7B991 CY7B992 Programmable Skew Clock Buffer Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 ps maximum ■ 3.75 MHz to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns


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    PDF CY7B991 CY7B992 CY7B992

    7B991

    Abstract: CY7B991 CY7B992 MS2525
    Text: CY7B991 CY7B992 Programmable Skew Clock Buffer Features functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can


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    PDF CY7B991 CY7B992 CY7B991 CY7B992 80-MHz 7B991 MS2525

    CY7B991

    Abstract: CY7B992
    Text: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All Output Pair Skew <100 ps Typical 250 ps maximum ■ 3.75 MHz to 80 MHz Output Operation ■ User Selectable Output Functions ❐ Selectable Skew to 18 ns ❐ Inverted and Non-inverted


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    PDF CY7B991 CY7B992 CY7B991 CY7B992

    2T transistor surface mount

    Abstract: phase shift oscillator Cypress handbook Cypress Semiconductor application handbook MECL System Design Handbook transistor 2Fn dip guard capacitor motorola C 547 motorola mecl system design handbook pll pcb design
    Text: fax id: 3603 Everything You Need to Know About CY7B991/2 RoboClock , CY7B9911 (RoboClock+), and CY7B9910/20 (Robo Jr.) Introduction TEST The following application note provides a detailed description of the CY7B991, CY7B9911, and CY7B992 Programmable Skew Clock Buffers (PSCB). It also provides an overview of


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    PDF CY7B991/2 CY7B9911 CY7B9910/20 CY7B991, CY7B9911, CY7B992 2T transistor surface mount phase shift oscillator Cypress handbook Cypress Semiconductor application handbook MECL System Design Handbook transistor 2Fn dip guard capacitor motorola C 547 motorola mecl system design handbook pll pcb design

    CY7B991-5JC

    Abstract: CY7B991 7B991 CY7B992
    Text: fax id: 3515 1CY 7B9 92 CY7B991 CY7B992 Programmable Skew Clock Buffer PSCB Features functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can


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    PDF CY7B991 CY7B992 CY7B991 CY7B992 80-MHz CY7B991-5JC 7B991

    Untitled

    Abstract: No abstract text available
    Text: CY7B991 CY7B992 Programmable Skew Clock Buffer Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 ps maximum ■ 3.75 MHz to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns


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    PDF CY7B991 CY7B992 32-pin CY7B991 CY7B992

    Untitled

    Abstract: No abstract text available
    Text: QS5991 QS5992 QS5993 Programmable Skew PLL Clock Driver Q Q uality TurboClock S e m ic o n d u c t o r , I n c . FEATURES/BENEFITS DESCRIPTION • • • The QS599X family is a high fanout PLL based clock driver intended for high performance computing and


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    PDF QS5991 QS5992 QS5993 QS599X whiletheQS5993 CY7B99X MDSC-00014-07

    Untitled

    Abstract: No abstract text available
    Text: pyi Low Skew Tm\ ^ QS59920 PLL Clock Driver Sem iconductor, Inc. T u rb o Q o c K ' p r e l im in a r y J r . FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge synchronization


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    PDF QS59920 200ps 250ps 15MHz 100MHz QS599xO S59910: QS59920: QS599xO-2: 250ps

    Untitled

    Abstract: No abstract text available
    Text: L0WSkew PLL Clock Driver S5992S advance T u rb O d O C k " J r. Q u a lit y S e m ic o n d u c t o r , I n c . INFORMATION FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge


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    PDF S5992S 200ps 250ps 100MHz QS599xO QS59910: QS59920: QS599xO-2: QS599xO-5:

    Untitled

    Abstract: No abstract text available
    Text: 1 Q uality Semiconductor , I nc . QS59910 QS59920 Low Skew PLL Clock Driver TurboClock Jr. FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Selectable positive or negative edge synchronization • Synchronous output enable • Output frequency: 15MHz to 110MHz


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    PDF QS59910 QS59920 QS59920 QS599X0 CY7B99X0 CY7B99Xcompatibility) MDSC-00027-05

    TP 401-400

    Abstract: CY7B9910 CY7B9920 QS59910 QS59920
    Text: ff i ^ q u a l it y Low Skew PLL Clock Driver SifiSIS QS59920 advance TurboClock Jr. in f o r m a t io n S e m ic o n d u c t o r , I n c . FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge


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    PDF qs59920 200ps 250ps 15MHz 100MHz QS599xO QS59910: QS59920: QS599xO-2: TP 401-400 CY7B9910 CY7B9920 QS59910 QS59920

    Untitled

    Abstract: No abstract text available
    Text: CYPRESS SEMICONDUCTOR b5E T> 2 5 0 ^ 2 QQ1Q7T2 CYP CY7B991 CY7B992 PRELIMINARY CYPRESS SEMICONDUCTOR TÔ2 P rogram m ab le Skew C lock B u ffer P S C B Functional Description • Output pair skew <100 ps typical (250 max.) • All outputs skew <250 ps typical


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    PDF CY7B991 CY7B992 T-90-20

    tb99

    Abstract: 005133a 0021336 CY78991 5 CY7B991 CY7B992 LOW11 RMS141
    Text: fax id: 3515 CY7B991 CY7B992 CYPRESS Programmable Skew Clock Buffer PSCB Features • All output pair skew <100 ps typical (250 max.) • 3.75- to 80-MHz output operation • User-selectable output functions — Selectable skew to 18 ns — Inverted and non-inverted


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    PDF CY7B991 CY7B992 80-MHz 32-pin CY7B992 tb99 005133a 0021336 CY78991 5 LOW11 RMS141