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    CY2SSTU32864

    Abstract: Q11A Q13A Q15-25 CY2SSTU32864BVXIT CY2SSTU32864BVXI BA96A t1 96x
    Text: PRELIMINARY CY2SSTU32864 1.8V, 25-bit 1:1 or 14-bit (1:2) JEDEC-Compliant Data Register Features • • • • • • Operating frequency: DC to 500 MHz Supports DDRII SDRAM Two operations modes: 25 bit (1:1) and 14 bit (1:2) 1.8V operation Fully JEDEC-compliant


    Original     		PDF CY2SSTU32864 25-bit 14-bit 96-ball CY2SSTU32864 Q11A Q13A Q15-25 CY2SSTU32864BVXIT CY2SSTU32864BVXI BA96A t1 96x