h22 8-pin
Abstract: J68 10A PL-20A DC3BE J119 J1266 1J44 PL34A JITo-2-dc3 J127
Text: ORLI10G ver. 1.5 1 01/29/03 Lattice Semiconductor Corp SECTION PAGE LAYOUT OF ORLI10G BOARD: 3 CONNECTORS AND JUMPERS J1 TO J127: 4 CONNECTORS CON1 TO CON5: 18 ADJUSTABLE RESISTORS: 22 ORLI10G ver. 1.5 2 01/29/03 Lattice Semiconductor Corp Layout of ORLI10G board:
|
Original
|
PDF
|
ORLI10G
ORLI10G:
h22 8-pin
J68 10A
PL-20A
DC3BE
J119
J1266
1J44
PL34A
JITo-2-dc3
J127
|
452-pin
Abstract: BCM8110 BCM8111 BCM8112 6 to 64 demux
Text: BCM8112 PRODUCT Brief 1 6 - B I T LV D S A N D 6 4 - B I T LV P E C L I N T E R FA C E B C M 8 1 1 2 F E AT U R E S 64:16 MUX with single-ended LVPECL • 155.52/166.65-Mbps data inputs and LVDS S U M M A R Y O F Compliant with industry standards such as: Optical
|
Original
|
PDF
|
BCM8112
65-Mbps
45-Mbps
OC-192
64-bit
16-bit
BCM8110/8111
8112-PB01-R-8
452-pin
BCM8110
BCM8111
BCM8112
6 to 64 demux
|
Untitled
Abstract: No abstract text available
Text: Preliminary Data Sheet May 2002 TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Features Description • Same functionality as TSWC01622 with reduced jitter specifications ■ Fully integrated clock synthesis ■ Clock or system sync protection switching
|
Original
|
PDF
|
TSWC03622
DS02-239HSPL
|
Untitled
Abstract: No abstract text available
Text: Data Advisory October 25, 2002 TSWC01622/TSWC02622/TSWC03622/TSYN01622 Device Advisory for Version 1.1 of the Device Reference data sheets October 2002, TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet DS02-237HSPL, TSWC02622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection
|
Original
|
PDF
|
TSWC01622/TSWC02622/TSWC03622/TSYN01622
TSWC01622
DS02-237HSPL,
TSWC02622
DS02-238HSPL)
TSWC03622
DS02-308HSPL,
TSYN01622
DS02-289HSPL)
TSWC0x622/TSYN01622
|
T400 clock
Abstract: TSWC01622 TSWC02622 TSWC03622 TSYN01622
Text: Data Advisory October 25, 2002 TSWC01622/TSWC02622/TSWC03622/TSYN01622 Device Advisory for Version 1.1 of the Device Reference data sheets October 2002, TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet DS02-237HSPL, TSWC02622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection
|
Original
|
PDF
|
TSWC01622/TSWC02622/TSWC03622/TSYN01622
TSWC01622
DS02-237HSPL,
TSWC02622
DS02-238HSPL)
TSWC03622
DS02-308HSPL,
TSYN01622
DS02-289HSPL)
TSWC0x622/TSYN01622
T400 clock
|
570FAB000433DG
Abstract: 88E1111 si570 88E1111-B2 HDMI to SDI converter chip 88E1111-B2-CAAIC000 schematic diagram lcd monitor samsung 19-PIN HDMI CONNECTOR LT3025 LCM-S01602DSR/C
Text: Stratix IV GX FPGA Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com Document Version: Document Date: 2.0 November 2009 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
|
Original
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: FEATURES ● Integrated clock and data recovery unit ● High-speed clock output power-down option ● Extended multirate support for: ● Low-speed 4-Bit LVDS I/O • STS-3/STM-1, STS-12/STM-4, STS-48/STM-16, and FEC ● LOS detect with automatic Lock to Reference
|
Original
|
PDF
|
STS-12/STM-4,
STS-48/STM-16,
25Gb/s
50Gb/s)
0625Gb/s
125Gb/s)
800mW
G52396
VSC8145
|
19-PIN HDMI CONNECTOR
Abstract: 570FAB000433DG PC28F512P30BF schematic diagram of laptop motherboard 88E1111 Marvell PHY 88E1111 Datasheet marvel phy 88e1111 reference design Marvell PHY 88E1111 layout samsung lcd monitor power board schematic 88E1111 PHY registers map
Text: Stratix IV GX FPGA Development Board Reference Manual Stratix IV GX FPGA Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01043-2.2 Subscribe 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.
|
Original
|
PDF
|
MNL-01043-2
19-PIN HDMI CONNECTOR
570FAB000433DG
PC28F512P30BF
schematic diagram of laptop motherboard
88E1111
Marvell PHY 88E1111 Datasheet
marvel phy 88e1111 reference design
Marvell PHY 88E1111 layout
samsung lcd monitor power board schematic
88E1111 PHY registers map
|
vhdl code for manchester decoder
Abstract: manchester verilog decoder MIL-HDBK-1553A 1553b VHDL 1553b bu-63147 fpga 1553B SA30L Verilog implementation of a Manchester Encoder/Decoder
Text: v3.0 MIL-STD-1553B Remote Terminal Core1553BRT Pr od uc t S um m ary De vel opm en t Sy s te m In t e n d e d U s e • Complete 1553BRT Implementation, Implemented in an A54SX32A • 1553B Remote Terminal RT • DMA Backend Interface to External Memory
|
Original
|
PDF
|
MIL-STD-1553B
Core1553BRT
1553B
1553BRT
A54SX32A
1553B
vhdl code for manchester decoder
manchester verilog decoder
MIL-HDBK-1553A
1553b VHDL
bu-63147
fpga 1553B
SA30L
Verilog implementation of a Manchester Encoder/Decoder
|
T400 clock
Abstract: ck77 diagram TSWC01622 TSWC02622 TSWC03622 TSYN01622 ATM machine working circuit diagram CK51
Text: Data Advisory October 25, 2002 TSWC01622/TSWC02622/TSWC03622/TSYN01622 Device Advisory for Version 1.1 of the Device Reference data sheets October 2002, TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet DS02-237HSPL, TSWC02622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection
|
Original
|
PDF
|
TSWC01622/TSWC02622/TSWC03622/TSYN01622
TSWC01622
DS02-237HSPL,
TSWC02622
DS02-238HSPL)
TSWC03622
DS02-308HSPL,
TSYN01622
DS02-289HSPL)
TSWC0x622/TSYN01622
T400 clock
ck77 diagram
ATM machine working circuit diagram
CK51
|
Untitled
Abstract: No abstract text available
Text: VSC8146 Datasheet FEATURES ● STS-48/STM-16, FEC ● On-board FIFO ● Wide-ranging PLLs ● Equipment and Facility Loopback modes ● Exceeds Telcordia SONET jitter specifications ● Rx/Tx internal Loop Timing mode ● High-speed data I/O and clock outputs
|
Original
|
PDF
|
VSC8146
STS-48/STM-16,
800mW
100-pin
VSC8146
VMDS-10030
|
Untitled
Abstract: No abstract text available
Text: VSC6134 Datasheet Features ● ● ● ● ● ● ● ● ● ● Two ITU-T G.709-compliant processors GR253-compliant STS192 section and line processor OTU synchronous and asynchronous mapping 10 GbE transport with RMON MIB per IEEE 802.3 ITU-T G.975 Reed Solomon encoder and decoder
|
Original
|
PDF
|
VSC6134
709-compliant
GR253-compliant
STS192
16-bit
STS192/10
97-free
897-pin
VMDS-10185
VSC6134
|
Untitled
Abstract: No abstract text available
Text: VSC8147 Datasheet Features • • • • • • • STS-48/STM-16, FEC Wide-ranging PLLs Exceeds Telcordia SONET jitter specifications High-speed data I/O and clock outputs High-speed clock output power-down option Low-speed 4-bit LVDS I/O LOS and LOL detect with automatic Lock to
|
Original
|
PDF
|
VSC8147
STS-48/STM-16,
800mW
100-pin
VSC8147
G52397
|
fpga 1553B
Abstract: 1553b VHDL MIL-STD-1553B FPGA Actel 1553b RT MIL-STD-1553B ACTEL FPGA vhdl code manchester encoder mil 1553b Core1553BRT v3.1 1553 VHDL manchester verilog decoder
Text: Core1553BRT MIL-STD-1553B Remote Terminal Product Summary • Intended Use • 1553B Remote Terminal RT • DMA Backend Interface to External Memory • Direct Backend Interface to Devices • Space and Avionic Applications • Supports MIL-STD 1553B •
|
Original
|
PDF
|
Core1553BRT
MIL-STD-1553B
1553B
1553B
1553BRT
A54SX32A
fpga 1553B
1553b VHDL
MIL-STD-1553B FPGA
Actel 1553b
RT MIL-STD-1553B ACTEL FPGA
vhdl code manchester encoder
mil 1553b
Core1553BRT v3.1
1553 VHDL
manchester verilog decoder
|
|
|
622-MHz
Abstract: 10gb TX drive vsc9271 VSC81
Text: FEATURES ● Integrated clock and data recovery unit ● High-speed clock output power-down option ● Extended multirate support for: ● Low-speed 4-Bit LVDS I/O • STS-3/STM-1, STS-12/STM-4, STS-48/STM-16, and FEC ● LOS detect with automatic Lock to Reference
|
Original
|
PDF
|
STS-12/STM-4,
STS-48/STM-16,
25Gb/s
50Gb/s)
0625Gb/s
125Gb/s)
800mW
156-pin
21x21x1
G52396
622-MHz
10gb TX drive
vsc9271
VSC81
|
Untitled
Abstract: No abstract text available
Text: VSC8142 Data Sheet FEATURES ● Integrated clock and data recovery ● Extended multirate support for: • • • • STS-3/STM-1, STS-12/STM-4, STS-48/STM-16, and FEC Gigabit Ethernet 1.25Gb/s and 2.50Gb/s Fibre Channel (1.0625Gb/s and 2.125Gb/s) Fast Ethernet
|
Original
|
PDF
|
VSC8142
16-bit
STS-12/STM-4,
STS-48/STM-16,
25Gb/s
50Gb/s)
0625Gb/s
125Gb/s)
700mW
G52395
|
Untitled
Abstract: No abstract text available
Text: VSC8142-03 and VSC8142-04 Datasheet FEATURES ● Integrated clock and data recovery ● Extended multirate support for: • STS-3/STM-1, STS-12/STM-4, STS-48/STM-16, and FEC ● Low-speed 16-bit single-ended or differential LVPECL I/O ● Low-speed bit-order swap MSB/LSB
|
Original
|
PDF
|
VSC8142-03
VSC8142-04
16-bit
STS-12/STM-4,
STS-48/STM-16,
CLK155
VMDS-10161
VSC8142VR-03
VSC8142VR-04
208-pin,
|
CK77
Abstract: No abstract text available
Text: Advance Data Sheet June 20, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 1 Introduction • Throughout this document references are made to the following application notes: ■ ■ ■ ■ 622.08 MHz 51.84 MHz 34.368 MHz 19.44 MHz 4.096 MHz 1.544 MHz
|
Original
|
PDF
|
TSYN03622
OC-12:
TSWC01622
TSWC03622/TSYN03622
TSWC01622/TSYN01622
DS03-130HSPL
CK77
|
ck77 diagram
Abstract: No abstract text available
Text: Data Advisory October 25, 2002 TSWC01622/TSWC02622/TSWC03622/TSYN01622 Device Advisory for Version 1.1 of the Device Reference data sheets October 2002, TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet DS02-237HSPL, TSWC02622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection
|
Original
|
PDF
|
TSWC01622/TSWC02622/TSWC03622/TSYN01622
TSWC01622
DS02-237HSPL,
TSWC02622
DS02-238HSPL)
TSWC03622
DS02-308HSPL,
TSYN01622
DS02-289HSPL)
TSWC0x622/TSYN01622
ck77 diagram
|
Marvell PHY 88E1111 Datasheet
Abstract: Marvell PHY 88E1111 layout 88E1111 PC28F512P30BF schematic diagram of laptop motherboard 88E1111 PHY registers map 88e1111-b2 88E111 TS-A02SA-2-S100 programming 88E1111
Text: Arria II GX FPGA Development Board, 6G Edition Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com Document Version: Document Date: 1.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
|
Original
|
PDF
|
|
Marvell PHY 88E1111 Datasheet
Abstract: 88E1111 PHY registers map Marvell PHY 88E1111 layout 88E1111 TS-A02SA-2-S100 MT8HTF12864HY-800G1 schematic diagram of laptop motherboard Marvell 88E1111 marvell 88E1111 register RGMII Marvell 88E1111 specification
Text: Arria II GX FPGA Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com Document Version: Document Date: 1.1 October 2009 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
|
Original
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: VSC8142-03 and VSC8142-04 Datasheet Extended Multirate 16:1 SONET/SDH Transceiver with Integrated CRU/CMU ● Integrated clock and data recovery ● Extended multirate support for: • STS-3/STM-1, STS-12/STM-4, STS-48/STM-16, and FEC ● Low-speed 16-bit single-ended or differential
|
Original
|
PDF
|
VSC8142-03
VSC8142-04
16-bit
STS-12/STM-4,
STS-48/STM-16,
CLK155
VMDS-10161
VSC8142VR-03
VSC8142VR-04
208-pin,
|
Untitled
Abstract: No abstract text available
Text: Preliminary Data Sheet June 11, 2003 TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch 1 Introduction The last issue of this data sheet was September 16, 2002. A revision history is included in Section 23, Revision History, on page 75. Red change bars have been installed on
|
Original
|
PDF
|
TSWC01622
DS03-117HSPL
DS02-237HSPL)
|
TADM04622
Abstract: TDAT04622 TMXF28155 TSI-16 TSWC01622 TSWC03622 f2021
Text: a'e re AdLib OCR Evaluation systems Preliminary Data Sheet May 2002 TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Features Description . Same functionality as TSWC01622 with reduced jitter specifications The Agere Systems TSWC03622 is designed for a
|
Original
|
PDF
|
TSWC03622
TSWC01622
DS02-239HS
TADM04622
TDAT04622
TMXF28155
TSI-16
f2021
|