CES7002A
Abstract: No abstract text available
Text: CES7002A March 1998 N-Channel Enhancement Mode Field Effect Transistor FEATURES D 60V , 0.28A , RDS ON =2 Ω @VGS=10V. RDS(ON)=3 Ω @VGS=5V. High dense cell design for low RDS(ON). Rugged and reliable. 7 SOT-23 Package. G SOT-23 D S S G ABSOLUTE MAXIMUM RATINGS (TA=25 C unless otherwise noted)
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CES7002A
OT-23
OT-23
CES7002A
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AIC1383
Abstract: AIC1383CSTR AIC1383PSTR CES7002A MS-012AA
Text: AIC1383 1.5A Termination Regulator FEATURES DESCRIPTION 1.5A Source and Sink Current Ability AIC1383 linear regulator is designed to achieve 1.5A source and sink current while regulating an output voltage to within 25mV. Support DDR1 1.25VTT and DDR2 (0.9VTT)
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AIC1383
AIC1383
25VTT)
AIC1383CSTR
AIC1383PSTR
CES7002A
MS-012AA
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6142E
Abstract: elektronik DDR SP2996B XRP6142EL0-5-F FDS6570
Text: X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination March 2010 Rev. 1.0.0 GENERAL DESCRIPTION APPLICATIONS The XRP6142 is a synchronous step down switching controller for over 15 Amps point-ofloads converters and optimized to generate
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XRP6142
6142E
elektronik DDR
SP2996B
XRP6142EL0-5-F
FDS6570
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AIC1383B
Abstract: AIC1383BCE5TR AIC1383BPE5TR CES7002A TO263-3 package DS-1383
Text: AIC1383B 3A Termination Regulator FEATURES DESCRIPTION 3A Source and Sink Current Ability AIC1383B linear regulator is designed to achieve 3A source and sink current while regulating an output voltage to within 45mV. Support DDR1 1.25VTT and DDR2 (0.9VTT)
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AIC1383B
AIC1383B
25VTT)
AIC1383BCE5TR
AIC1383BPE5TR
CES7002A
TO263-3 package
DS-1383
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AIC1383A
Abstract: CES7002A MS-012AA 1401 SOP-8
Text: AIC1383A 2A Termination Regulator FEATURES DESCRIPTION 2A Source and Sink Current Ability AIC1383A linear regulator is designed to Support DDR1 1.25VTT and DDR2 (0.9VTT) Requirements achieve 2A source and sink current while regulating an output voltage to within 20mV.
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AIC1383A
AIC1383A
25VTT)
CES7002A
MS-012AA
1401 SOP-8
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SP2996B
Abstract: 470uF 25V TANT REGULATOR 2A SP2996BEN CES7002A
Text: SP2996B 2 Amp DDR Bus Termination Regulator FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection ■ Integrated Power MOSFETs
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SP2996B
25VTT)
SP2996B
Aug16-05
SP2996BEN
SP2996BEN/TR
SP2996BEN-L/TR
470uF 25V TANT
REGULATOR 2A
SP2996BEN
CES7002A
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Untitled
Abstract: No abstract text available
Text: AIC1383A 2A Termination Regulator FEATURES DESCRIPTION 2A Source and Sink Current Ability AIC1383A linear regulator is designed to achieve 2A source and sink current while regulating an output voltage to within 20mV. Support DDR1 1.25VTT and DDR2 (0.9VTT)
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AIC1383A
AIC1383A
25VTT)
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Untitled
Abstract: No abstract text available
Text: Preliminary SP2996B 2A Bus Termination Regulator VIN 1 FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection
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SP2996B
25VTT)
SP2996B
SP2996BEN/TR
SP2996BEN-L-/TR
935-7600m
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Untitled
Abstract: No abstract text available
Text: AIC1383A 2A Termination Regulator FEATURES DESCRIPTION 2A Source and Sink Current Ability AIC1383A linear regulator is designed to Support DDR1 1.25VTT and DDR2 (0.9VTT) Requirements achieve 2A source and sink current while regulating an output voltage to within 20mV.
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AIC1383A
AIC1383A
25VTT)
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AIC1383B
Abstract: CES7002A MS-012AA
Text: AIC1383B 3A Termination Regulator FEATURES DESCRIPTION 3A Source and Sink Current Ability AIC1383B linear regulator is designed to Support DDR1 1.25VTT and DDR2 (0.9VTT) Requirements achieve 3A source and sink current while Low Output Voltage Offset, ±20mV
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AIC1383B
AIC1383B
25VTT)
CES7002A
MS-012AA
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Untitled
Abstract: No abstract text available
Text: AIC1383 1.5A Termination Regulator FEATURES DESCRIPTION 1.5A Source and Sink Current Ability AIC1383 linear regulator is designed to Support DDR1 1.25VTT and DDR2 (0.9VTT) Requirements achieve 1.5A source and sink current while regulating an output voltage to within 25mV.
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AIC1383
AIC1383
25VTT)
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AIC1383
Abstract: AIC1383CSTR AIC1383PSTR CES7002A
Text: AIC1383 1.5A Termination Regulator FEATURES DESCRIPTION 1.5A Source and Sink Current Ability AIC1383 linear regulator is designed to achieve 1.5A source and sink current while regulating an output voltage to within 25mV. Support DDR1 1.25VTT and DDR2 (0.9VTT)
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AIC1383
AIC1383
25VTT)
AIC1383CSTR
AIC1383PSTR
CES7002A
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Untitled
Abstract: No abstract text available
Text: AIC1383 1.5A Termination Regulator FEATURES DESCRIPTION 1.5A Source and Sink Current Ability AIC1383 linear regulator is designed to achieve 1.5A source and sink current while regulating an output voltage to within 25mV. Support DDR1 1.25VTT and DDR2 (0.9VTT)
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AIC1383
AIC1383
25VTT)
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Untitled
Abstract: No abstract text available
Text: AIC1383B 3A Termination Regulator FEATURES DESCRIPTION 3A Source and Sink Current Ability AIC1383B linear regulator is designed to achieve 3A source and sink current while regulating an output voltage to within 45mV. Support DDR1 1.25VTT and DDR2 (0.9VTT)
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AIC1383B
AIC1383B
25VTT)
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Untitled
Abstract: No abstract text available
Text: AIC1383B 3A Termination Regulator FEATURES DESCRIPTION 3A Source and Sink Current Ability AIC1383B linear regulator is designed to achieve 3A source and sink current while regulating an output voltage to within 45mV. Support DDR1 1.25VTT and DDR2 (0.9VTT)
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AIC1383B
AIC1383B
25VTT)
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jedec MS-012-AA
Abstract: SP2996BEN CES7002A SP2996B
Text: Advanced SP2996B 2A Bus Termination Regulator VIN 1 FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection
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SP2996B
25VTT)
SP2996B
SP2996BEN/TR
SP2996BEN-L-/TR
935-7600m
jedec MS-012-AA
SP2996BEN
CES7002A
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DS-1383
Abstract: 470PF 47PF AIC1383 AIC1383CSTR CES7002A
Text: AIC1383 1.5A Termination Regulator FEATURES DESCRIPTION z 1.5A Source and Sink Current Ability AIC1383 linear regulator is designed to z Support DDR1 1.25VTT and DDR2 (0.9VTT) Requirements achieve 1.5A source and sink current while z Low Output Voltage Offset, r20mV
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AIC1383
AIC1383
25VTT)
DS-1383
470PF
47PF
AIC1383CSTR
CES7002A
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JESD8-15a
Abstract: ITT RZ2 SP2996 SP2996B CES7002A SP2996BEN TRANSISTOR HANDLING 2A
Text: SP2996B 2 Amp DDR Bus Termination Regulator FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection ■ Integrated Power MOSFETs
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SP2996B
25VTT)
SP2996B
188uF
JESD8-15a
ITT RZ2
SP2996
CES7002A
SP2996BEN
TRANSISTOR HANDLING 2A
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CES7002A
Abstract: LL4001
Text: CES7002A March 1998 N-Channel Enhancement Mode Field Effect Transistor FEATURES • 6 0 V , 0 .2 8 A , R ds on =2Q R ds(on)=3Q @ V gs =1 0V. @ V gs =5V. • High dense cell design for low R ds (on ).
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CES7002A
OT-23
OT-23
CES7002A
LL4001
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