CD74HC73 Search Results
CD74HC73 Result Highlights (3)
Part |
ECAD Model |
Manufacturer |
Description |
Download |
Buy
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| CD74HC73MT |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 |
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| CD74HC73E |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 |
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| CD74HC73M96 |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 |
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CD74HC73 Price and Stock
Texas Instruments CD74HC73M96IC FF JK TYPE DBL 1-BIT 14-SOIC |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC73M96 | Reel | 2,500 | 2,500 |
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CD74HC73M96 | 7,220 |
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CD74HC73M96 | 2,168 | 53 |
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CD74HC73M96 | Cut Strips | 2,168 | 6 Weeks | 1 |
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CD74HC73M96 | 71 | 1 |
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CD74HC73M96 | 1,160 |
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CD74HC73M96 | 42 |
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Get Quote | |||||||
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CD74HC73M96 | 3,000 |
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Texas Instruments CD74HC73MIC FF JK TYPE DBL 1-BIT 14-SOIC |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC73M | Tube | 160 | 1 |
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CD74HC73M | 3,529 | 544 |
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CD74HC73M | Bulk | 1 |
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CD74HC73M | 6,754 | 1 |
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CD74HC73M | 7,400 |
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Texas Instruments CD74HC73MTIC FF JK TYPE DBL 1-BIT 14-SOIC |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC73MT | Digi-Reel | 15 | 1 |
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CD74HC73MT | 15 |
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CD74HC73MT | 4,500 |
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Rochester Electronics LLC CD74HC73MIC FF JK TYPE DBL 1-BIT 14-SOIC |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC73M | Bulk | 523 |
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Rochester Electronics LLC CD74HC73EIC FF JK TYPE DBL 1-BIT 14-PDIP |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC73E | Bulk | 629 |
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CD74HC73 Datasheets (38)
Part |
ECAD Model |
Manufacturer |
Description |
Curated |
Datasheet Type |
PDF |
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| CD74HC73 |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73 |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73E |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73E |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73E |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73E |
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CD74HC73 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73E | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73E96 |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73EE4 |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73EE4 |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73EE4 |
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CD74HC73 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73EG4 |
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Integrated Circuits (ICs) - Logic - Flip Flops - IC FF JK TYPE DUAL 1BIT 14DIP | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73M |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73M |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| CD74HC73M |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73M |
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CD74HC73 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73M | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73M96 |
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HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73M96 |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC73M96 |
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CD74HC73 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CD74HC73 Datasheets Context Search
Catalog Datasheet |
Type |
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PDF |
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Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 HC/HCT107 | |
CD54HC73
Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
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HCT73 CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 CD54HC73 CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M HC73 | |
CD54HC73
Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
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HCT73 CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 CD54HC73 CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M HC73 | |
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Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 HC/HCT107 | |
CD54HC73
Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
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HCT73 CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 CD54HC73 CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M HC73 | |
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Contextual Info: CD74HC73, CD74HCT73 ^ Texas In s t r u m e n t s Data sheet acquired from Harris Semiconductor SCHS134 Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times |
OCR Scan |
CD74HC73, CD74HCT73 SCHS134 CD74HC73 CD74HCT73 | |
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Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 HC/HCT107 | |
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Contextual Info: CD74HC73, CD74HCT73 S E M I C O N D U C T O R Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The Harris CD74HC73 and CD74HCT73 utilize silicon gate |
Original |
CD74HC73, CD74HCT73 CD74HC73 CD74HCT73 HC/HCT107 74HCT 1-800-4-HARRIS | |
74HCT
Abstract: 74LS CD74HC73 CD74HC73E CD74HCT73 CD74HCT73E HC73
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HCT73 CD74HC73, CD74HCT73 SCHS134 CD74HC73 CD74HCT73 74HCT 74LS CD74HC73E CD74HCT73E HC73 | |
HS-134Contextual Info: CD74HC73, CD74HCT73 ^ Texas In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC HS134 Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times |
OCR Scan |
HS134 CD74HC73, CD74HCT73 CD74HC73 CD74HCT73 HC/HCT107 HS-134 | |
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Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 HC/HCT107 | |
CD54HC73
Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
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Original |
HCT73 CD54HC73, CD74HC73, CD74HCT73 SCHS134D CD74HCT73 CD54HC73 CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M HC73 | |
CD54HC73
Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
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HCT73 CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 CD54HC73 CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M HC73 | |
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Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 HC/HCT107 | |
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cd54hc73f
Abstract: CD54HC73 CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
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Original |
HCT73 CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 cd54hc73f CD54HC73 CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M HC73 | |
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Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 HC/HCT107 | |
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Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 HC/HCT107 | |
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Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 HC/HCT107 | |
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Contextual Info: ASSESS? CD74HC73, CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The Harris CD74HC73 and CD74HCT73 utilize silicon gate |
OCR Scan |
CD74HC73, CD74HCT73 CD74HC73 CD74HCT73 HC/HCT107 74HCT | |
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Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
HCT73 CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 | |
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Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 HC/HCT107 | |
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Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 HC/HCT107 | |
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Contextual Info: CD74HC73, CD74HCT73 fC l H A R R IS S E M I C O N D U C T O R Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features • Description Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The Harris CD74HC73 and CD74HCT73 utilize silicon gate |
OCR Scan |
CD74HC73, CD74HCT73 CD74HC73 CD74HCT73 HC/HCT107 74HCT 1-800-4-HARRIS | |
JK Flip-flopContextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
CD54HC73, CD74HC73, CD74HCT73 SCHS134E CD74HCT73 HC/HCT107 JK Flip-flop | |