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    C35B3 Search Results

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    C35B3 Price and Stock

    CTS Corporation 406C35B35M32800

    CRYSTAL 35.3280MHZ 13PF SMD
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    DigiKey 406C35B35M32800 Reel 1,000
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    Avnet Americas 406C35B35M32800 Reel 10 Weeks 1,000
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    Mouser Electronics 406C35B35M32800
    • 1 $1.03
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    Richardson RFPD 406C35B35M32800 1
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    Avnet Abacus 406C35B35M32800 Reel 12 Weeks 1,000
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    CTS Corporation 406C35B38M88000

    CRYSTAL 38.8800MHZ 13PF SMD
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    DigiKey 406C35B38M88000 Reel 1,000
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    Mouser Electronics 406C35B38M88000
    • 1 $0.88
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    • 100 $0.637
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    Richardson RFPD 406C35B38M88000 1
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    Avnet Abacus 406C35B38M88000 Reel 12 Weeks 1,000
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    CTS Corporation 405C35B33M00000

    CRYSTAL 33.0000MHZ 13PF SMD
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    DigiKey 405C35B33M00000 Reel 1,000
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    Avnet Americas 405C35B33M00000 Reel 8 Weeks 1,000
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    Mouser Electronics 405C35B33M00000
    • 1 $0.82
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    Richardson RFPD 405C35B33M00000 1
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    Avnet Abacus 405C35B33M00000 Reel 10 Weeks 1,000
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    CTS Corporation 445C35B30M00000

    CRYSTAL 30.0000MHZ 13PF SMD
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    DigiKey 445C35B30M00000 Reel 1,000
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    Mouser Electronics 445C35B30M00000
    • 1 $0.66
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    Avnet Abacus 445C35B30M00000 Reel 10 Weeks 1,000
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    CTS Corporation 405C35B32M00000

    CRYSTAL 32.0000MHZ 13PF SMD
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    DigiKey 405C35B32M00000 Reel 1,000
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    Mouser Electronics 405C35B32M00000 237
    • 1 $0.85
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    Bristol Electronics 405C35B32M00000 53
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    Richardson RFPD 405C35B32M00000 1
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    Avnet Abacus 405C35B32M00000 Reel 10 Weeks 1,000
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    C35B3 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CDAC10

    Abstract: No abstract text available
    Text: ANALOG IP BLOCK CDAC10 - CMOS 10-Bit D/A CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The CDAC10 is a 10-bit high-resolution high-speed CMOS digital-to-analog converter (DAC). The CDAC10 uses a segmented current steering architecture combined with a simple and fast decoding logic to achieve a very high


    Original     		PDF CDAC10 10-Bit C35B3 680pF 330pF

    lvds standard

    Abstract: LVDS_RX SOIC28 MA1014
    Text: ANALOG IP BLOCK LVDS_RX - CMOS LVDS Receiver DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The LVDS_RX is a differential line receiver designed for applications requiring high data rates. The device supports data rates up to 622Mb/s (311 MHz). The LVDS_RX accepts (350mV) differential input signals and


    Original     		PDF C35B3 622Mb/s 350mV) 08mm2, lvds standard LVDS_RX SOIC28 MA1014

    SCADC10

    Abstract: No abstract text available
    Text: ANALOG IP BLOCK SCADC10 - CMOS 10-Bit A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The SCADC10 is a complete analog to digital converter cell which operates from a single supply. It performs sampling, analog-to-digital conversion, generating a


    Original     		PDF SCADC10 10-Bit C35B3 500kS/s. 16mm2 10-Bit 500kS/s 300kHz) THS3001.

    F100K

    Abstract: SOIC28 transmitter 446 mhz Analog Delay Lines
    Text: ANALOG IP BLOCK PECL_TX - CMOS PECL Transmitter PROCESS C35B3 0.35um DATA SHEET DESCRIPTION The PECL_TX is a differential 3.3 V PECL transmitter featuring a transmission speed of 622 Mb/s with standard F100K levels (referred to the positive supply). Unlike other


    Original     		PDF C35B3 F100K SOIC28 transmitter 446 mhz Analog Delay Lines

    ADC1220

    Abstract: MS 1117 ADC EN16 AD711 AD8138
    Text: ANALOG IP BLOCK ADC1220 - CMOS 12-Bit Pipelined A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The ADC1220 is a high-speed pipeline ADC core cell achieving sampling rates up to 20 MS/s. A S/H circuit is built-in to provide low jitter noise and a fully differential


    Original     		PDF ADC1220 12-Bit C35B3 12-Bit AD8138 ADC1220 MS 1117 ADC EN16 AD711

    AD711

    Abstract: THS3001 DIN 3015
    Text: ANALOG IP BLOCK FLASH6 - CMOS 6-Bit FLASH A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The FLASH6 is a complete analog to digital converter cell which operates from a single supply. It performs sampling, analog-to-digital conversion, generating a


    Original     		PDF C35B3 100MS/s. 100MS/s 32MHz) THS3001. AD711 THS3001 DIN 3015

    F100K

    Abstract: SOIC28
    Text: ANALOG IP BLOCK PECL_RX - CMOS PECL Receiver PROCESS C35B3 0.35um FEATURES ! PECL_RX area: 0.1 mm2, ! size: x = 300 µm y = 340 µm PERXBIAS ! 3.3 V ±10% supply voltage ! 622 Mb/s transmission speed size: x = 382 µm y = 375 µm ! 1 ns max. propagation delay


    Original     		PDF C35B3 F100K SOIC28

    ADC1020

    Abstract: THS3001 AD1020 AD711 K4103
    Text: ANALOG IP BLOCK ADC1020 - CMOS 10-Bit Pipelined A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The AD1020 is a high-speed pipeline ADC core cell achieving sampling rates up to 20 MS/s. A S/H circuit is built-in to provide low jitter noise and an optional singleended to fully differential conversion. The reference


    Original     		PDF ADC1020 10-Bit C35B3 AD1020 57mm2 12MHz) THS3001. ADC1020 THS3001 AD711 K4103

    th 2047.5

    Abstract: CDAC12
    Text: ANALOG IP BLOCK CDAC12 - CMOS 12-Bit D/A CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The CDAC12 is a 12-bit high-resolution high-speed CMOS digital-toanalog converter (DAC). The CDAC12 uses a segmented current steering architecture combined with a simple and fast decoding logic to achieve a very high


    Original     		PDF CDAC12 12-Bit C35B3 680pF 330pF th 2047.5

    APRIO200P

    Abstract: No abstract text available
    Text: ANALOG IP BLOCK LVDS_RX - CMOS LVDS Receiver DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The LVDS_RX is a differential line receiver designed for applications requiring high data rates. The device supports data rates up to 1Gb/s (500MHz). The LVDS_RX accepts (350mV) differential input signals and


    Original     		PDF C35B3 500MHz) 350mV) APRIO200P

    AD711

    Abstract: SCADC12
    Text: ANALOG IP BLOCK SCADC12 - CMOS 12-Bit 4 Channel, Autocalibrating A/D CONVERTER PROCESS DESCRIPTION C35B3 0.35um The SCADC 12 is a complete analog to digital converter cell which operates from a single supply. It performs sampling, analog-to-digital conversion, generating a


    Original     		PDF SCADC12 12-Bit C35B3 500kHz. 12-Bit 500kS/s 300kHz) THS3001. AD711

    LVDS_RX

    Abstract: SOIC28 receiver LVDS_rx LVDS_TX backs
    Text: ANALOG IP BLOCK LVDS_TX - CMOS LVDS Transmitter DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The LVDS_TX is a differential line driver designed for applications requiring high data rates. The device supports data rates up to 622Mb/s (311 MHz). The LVDS_TX accepts CMOS input levels and translates


    Original     		PDF C35B3 622Mb/s 350mV) LVDS_RX SOIC28 receiver LVDS_rx LVDS_TX backs

    efp2

    Abstract: AD711 SCADC12F THS3001
    Text: ANALOG IP BLOCK SCADC12F - CMOS 12-Bit A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The SCADC12F is a complete analog to digital converter cell which operates from a single supply. It performs sampling, analog-to-digital conversion, generating a true 12 bit value in parallel form. The


    Original     		PDF SCADC12F 12-Bit C35B3 83mm2 12-Bit THS3001. efp2 AD711 THS3001

    140U

    Abstract: lvds_tx
    Text: ANALOG IP BLOCK LVDS_RX - CMOS LVDS Receiver DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The LVDS_RX is a differential line receiver designed for applications requiring high data rates. The device supports data rates up to 1Gb/s (500MHz). The LVDS_RX accepts (350mV) differential input signals and


    Original     		PDF C35B3 500MHz) 350mV) 140U lvds_tx

    C3953

    Abstract: No abstract text available
    Text: 1 1111111111111 111111 1 1111111111111 1 1111111111111 1 1111111111111 1 1 812345678889ABACDEFA8D9 8 888 88888888 88 88888888 8 8 A8C AB8C8 3DE"#$%&'8 ! !8 26*8)98CC8"#$8AABA9 2+,(-3,2(+.


    Original     		PDF 8889ABACDEFA 1234567812345678493A58BC3D19E3F 3DE14E31232 775B9 14B54E17 A58BC D19E3 3614B545 775B92- 14B54E1732984 C3953