ak36
Abstract: AR33 426 b34 AD38 AG39 ak38 an17 c33 AP 309 AU35 AB34
Text: PA-IPGA447-01 Map 1 24 47 70 93 115 137 159 178 192207222237252267281295317339361383405427 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B A D C F E H G K J M L P N T R V U Y AB AD AF AH AK AM AP AT AV
|
Original
|
PA-IPGA447-01
ak36
AR33
426 b34
AD38
AG39
ak38
an17 c33
AP 309
AU35
AB34
|
PDF
|
RTAX2000S
Abstract: RTAX1000S-SL cga 624 RTAX1000S RTAX250S RTAX2000 624 CCGA SL D8 E26 RTAX4000S CCGA
Text: RTAX-S/SL RadTolerant FPGAs Package Pin Assignments 208 207 206 205 160 159 158 157 208-Pin CQFP Pin 1 1 2 3 4 156 155 154 153 Ceramic Tie Bar 208-Pin CQFP 108 107 106 105 101 102 103 104 53 54 55 56 49 50 51 52 Figure 3-1 • 208-Pin CQFP Top View Note
|
Original
|
208-Pin
RTAX250S/SL
IO43PB2F2
IO76PB5F5/CLKGP
IO02NB0F0
RTAX2000S
RTAX1000S-SL
cga 624
RTAX1000S
RTAX250S
RTAX2000
624 CCGA
SL D8 E26
RTAX4000S
CCGA
|
PDF
|
AB244A
Abstract: R488A AD9361 AK2177 CMOS-9HD UPD65891 N526A PD65891 tqfp 64 thermal resistance nec PD65881
Text: Design Manual CMOS Gate Array, Embedded Array Package Ver. 4.0 Target Series CMOS-N5 Series CMOS-9HD Series CMOS-10HD Series EA-9HD Series Document No. A16400EJ4V0DM00 4th edition Date Published December 2004 NS CP(N) NEC Electronics Corporation 2002
|
Original
|
CMOS-10HD
A16400EJ4V0DM00
A16400EJ4V0DM
IR50-203-3-37
IR50-207-3-37
AB244A
R488A
AD9361
AK2177
CMOS-9HD
UPD65891
N526A
PD65891
tqfp 64 thermal resistance nec
PD65881
|
PDF
|
AX125
Abstract: FBGA 896 896-Pin
Text: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View Note For Package Manufacturing and Environmental information, visit Resource center at
|
Original
|
180-Pin
AX125
IO32NB3F3
IO59NB5F5
FBGA 896
896-Pin
|
PDF
|
729-Pin
Abstract: Axcelerator FPGAs AX125 IO126PB3F11 AG18 FBGA 896 896-Pin Axcelerator Family FPGAs
Text: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View Note For Package Manufacturing and Environmental information, visit Resource center at
|
Original
|
180-Pin
AX125
IO32NB3F3
IO59NB5F5
729-Pin
Axcelerator FPGAs
IO126PB3F11
AG18
FBGA 896
896-Pin
Axcelerator Family FPGAs
|
PDF
|
CCGA
Abstract: 896-Pin 624 CCGA AD 149 AE9 FBGA 63 AX125 FBGA 896
Text: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View v2.3 3-1 Axcelerator Family FPGAs 180-Pin CSP 180-Pin CSP AX125 Function Pin Number
|
Original
|
180-Pin
AX125
IO32NB3F3
IO59NB5F5
CCGA
896-Pin
624 CCGA
AD 149 AE9
FBGA 63
FBGA 896
|
PDF
|
ap1448
Abstract: 45x45 bga an6169 RXFD65 Rxd07 734 B34 8B10B PD98431 C3258 709 B34
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD98433 TM 10/100/1000 Mbps Ethernet Controller The µPD98433 is a 10/100/1000 Mbps Ethernet controller with eight-port internal Media Access Control MAC function that complies with the IEEE Standard 802.3 1998 Edition.
|
Original
|
PD98433
PD98433
128-bit
ap1448
45x45 bga
an6169
RXFD65
Rxd07
734 B34
8B10B
PD98431
C3258
709 B34
|
PDF
|
g30 nec 222
Abstract: g33 704 AP1650 FC 530 AN8171 734 B34
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD98433 10/100/1000 Mbps EthernetTM Controller The µPD98433 is a 10/100/1000 Mbps Ethernet controller with eight-port internal Media Access Control MAC function that complies with the IEEE Standard 802.3 1998 Edition.
|
Original
|
PD98433
PD98433
128-bit
g30 nec 222
g33 704
AP1650
FC 530
AN8171
734 B34
|
PDF
|
BCPZ
Abstract: 48-PIN QFP048-P-0707 h5431 220-P-blk
Text: LZ95D71 M LZ95D71 M Timing Pulse Generator LSI for CCD DESCRIPTION PIN CONNECTIONS The U95D71 M is a CMOS timing generator LSI which provides timing pulses used to drive a CCD area sensor, in combination with the SSG LSI LZ95D52/M . FEATURES ● Switchable between 410000 pixels CCD and
|
Original
|
LZ95D71
U95D71
LZ95D52/M)
LZ95D71M
120nsl
\20ns150ys
BCPZ
48-PIN
QFP048-P-0707
h5431
220-P-blk
|
PDF
|
56 pin edac connector
Abstract: PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical
Text: v2.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
|
Original
|
TM1019
56 pin edac connector
PCB footprint cqfp 132
Silicon Sculptor II
ACTEL CCGA 624 mechanical
|
PDF
|
56 pin edac connector
Abstract: RTAX1000 edac 96 pin edac connector 292 CCGA
Text: v2.1 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
|
Original
|
TM1019
56 pin edac connector
RTAX1000
edac 96 pin edac connector
292 CCGA
|
PDF
|
RTAX2000
Abstract: rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3
Text: v5.1 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg
|
Original
|
TM1019
RTAX2000
rtax4000
CDB 455 C34
IO358
DIODE SMD V05
128X3
|
PDF
|
CQ352-FPGA
Abstract: RTAX1000s-cq RTAX4000S RTAX2000 RTAX2000S-CQ352 FPGA Application Note schematic 324 CDB 455 C34 rtax4000 AP3433
Text: v4.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
|
Original
|
TM1019
CQ352-FPGA
RTAX1000s-cq
RTAX4000S
RTAX2000
RTAX2000S-CQ352
FPGA Application Note
schematic 324
CDB 455 C34
rtax4000
AP3433
|
PDF
|
RTAX2000S
Abstract: CDB 455 C34 RTAX1000S-CQ352 RTAX2000S-CQ352
Text: v3.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
|
Original
|
TM1019
RTAX2000S
CDB 455 C34
RTAX1000S-CQ352
RTAX2000S-CQ352
|
PDF
|
|
|
LGA 478 SOCKET PIN LAYOUT
Abstract: RTAX2000
Text: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg
|
Original
|
TM1019
LGA 478 SOCKET PIN LAYOUT
RTAX2000
|
PDF
|
624 CCGA
Abstract: CCGA ACTEL CCGA 624 mechanical
Text: v2.2 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
|
Original
|
TM1019
624 CCGA
CCGA
ACTEL CCGA 624 mechanical
|
PDF
|
b h21
Abstract: No abstract text available
Text: Revision 18 Axcelerator Family FPGAs Leading-Edge Performance • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
608-bit
b h21
|
PDF
|
SMJ320C30
Abstract: SMJ320C40
Text: SMJ320C40 DIGITAL SIGNAL PROCESSOR SGUS017A – OCTOBER 1993 – REVISED MAY 1996 D D D D D D D D D D D D – 55°C to 125°C Operating Temperature Range; QML Processing Highest Performance Floating-Point Digital Signal Processor DSP – ’C40-50: 40-ns Instruction Cycle Time:
|
Original
|
SMJ320C40
SGUS017A
C40-50:
40-ns
C40-40:
50-ns
C40-33:
60-ns
IEEE-745
SMJ320C30
SMJ320C30
SMJ320C40
|
PDF
|
ld18 st
Abstract: TMS 3834 SMJ320C30 SMJ320C40
Text: SMJ320C40 DIGITAL SIGNAL PROCESSOR SGUS017A – OCTOBER 1993 – REVISED MAY 1996 D D D D D D D D D D D D – 55°C to 125°C Operating Temperature Range; QML Processing Highest Performance Floating-Point Digital Signal Processor DSP – ’C40-50: 40-ns Instruction Cycle Time:
|
Original
|
SMJ320C40
SGUS017A
C40-50:
40-ns
C40-40:
50-ns
C40-33:
60-ns
IEEE-745
SMJ320C30
ld18 st
TMS 3834
SMJ320C30
SMJ320C40
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H – OCTOBER 1993 – REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL–PRF–38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges:
|
Original
|
SMJ320C40,
TMP320C40
SGUS017H
C40-60:
33-ns
C40-50:
40-ns
C40-40:
50-ns
|
PDF
|
ld18 st
Abstract: No abstract text available
Text: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL−PRF−38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges:
|
Original
|
SMJ320C40,
TMP320C40
SGUS017H
MIL-PRF-38535
C40-60:
33-ns
C40-50:
40-ns
C40-40:
50-ns
ld18 st
|
PDF
|
G330240
Abstract: M330245 H330241 L330244 F330239 K330243 D330237 F210156 Z330210 B330235
Text: * * A < ► Semiconductor Fuses European Fuses DIN 00 Fuses 6,9 gRB-URB - 6 URB 690 V ~ gRB-URB from 16 to 450 A Size: 00 EXTREMELY HIGH INTERRUPTING RATING FUSES: PROTECTION OF PO W ER SEM ICO NDUCTORS AS PER IEC STANDARD 269.1 AN D 4 690 V VOLTAGE RATING
|
OCR Scan
|
43653/00C
G330240
M330245
H330241
L330244
F330239
K330243
D330237
F210156
Z330210
B330235
|
PDF
|
SN74ACT7803
Abstract: SN74ACT7805 SN74ACT7813 SN74ALVC7803 SN74ALVC7805 SN74ALVC7813
Text: SN74ALVC7803, SN74ALVC7805, SN74ALVC7813 512x 18, 256x 18, 64x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS436 - JUNE 1994 DL PACKAGE TOP VIEW Free-Running Read and Write Clocks Can Be Asynchronous or Coincident RESET D17 D16 D15 D14 D13 D12 D11 Read and Write Operations Synchronized to
|
OCR Scan
|
SN74ALVC7803,
SN74ALVC7805,
SN74ALVC7813
SCAS436
50-pF
SN74ACT7803,
SN74ACT7805
SN74ACT7813
D1D1D13
SN74ACT7803
SN74ACT7813
SN74ALVC7803
SN74ALVC7805
SN74ALVC7813
|
PDF
|
a20202
Abstract: 25p28 84 PIN CERAMIC QUAD FLAT PACK TEXAS INSTRUMENTS LA7292 325-pin 436-Pin ld25 cv ot 112 S20C40 ansi y32
Text: SMJ320C40 DIGITAL SIGNAL PROCESSOR SGUS017 - OCTOBER 1993 -55°C to 125°C Operating Temperature Range; Class B Processing Highest Performance Floating-Point DSP - 50-ns Instruction Cycle Time: 220 MOPS, 40 MFLOPS, 20 MIPS, 256 Mbytes/s - 60-ns Instruction Cycle Time:
|
OCR Scan
|
SMJ320C40
SGUS017
50-ns
60-ns
SMJ320C30
40-Bit
32-Bit
a20202
25p28
84 PIN CERAMIC QUAD FLAT PACK TEXAS INSTRUMENTS
LA7292
325-pin
436-Pin
ld25 cv
ot 112
S20C40
ansi y32
|
PDF
|