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    Untitled

    Abstract: No abstract text available
    Text: CY7C1444AV33 36-Mbit 1 M x 36 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Functional Description Features • Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation


    Original     		PDF CY7C1444AV33 36-Mbit 167-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1444AV33 CY7C1445AV33 36-Mbit 1M x 36/2M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation


    Original     		PDF CY7C1444AV33 CY7C1445AV33 36-Mbit 36/2M 250-MHz CY7C1444AV33, CY7C1445AV33 l2006-2010.

    Untitled

    Abstract: No abstract text available
    Text: CY7C1480V33 CY7C1482V33 CY7C1486V33 ADVANCE INFORMATION 2M x 36/4M x 18/1M x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 300, 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate


    Original     		PDF CY7C1480V33 CY7C1482V33 CY7C1486V33 36/4M 18/1M CY7C1480V33/CY7C1482V33/CY7C1482V33

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states


    Original     		PDF CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 36/4M 18/1M 250-MHz 200-MHz 167-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1441AV25 CY7C1443AV25 CY7C1447AV25 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common I/O • 2.5V core power supply • 2.5V/1.8V I/O power supply


    Original     		PDF CY7C1441AV25 CY7C1443AV25 CY7C1447AV25 36-Mbit 36/2M 18/512K 133-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common I/O • 3.3V core power supply • 2.5V or 3.3V I/O power supply


    Original     		PDF CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 36-Mbit 36/2M 18/512K 133-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY 72-Mbit 2M x 36/4M x 18/1M x 72 Pipelined Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200,167 MHz • Registered inputs and outputs for pipelined operation


    Original     		PDF CY7C1480V33 CY7C1482V33 CY7C1486V33 72-Mbit 36/4M 18/1M 250-MHz 200-MHz 167-MHz

    165BGA

    Abstract: No abstract text available
    Text: CY7C1484V25 CY7C1485V25 PRELIMINARY 72-Mbit 2M x 36/4M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation


    Original     		PDF CY7C1484V25 CY7C1485V25 72-Mbit 36/4M 250-MHz 200-MHz 167-MHz 165FBGA 119-BGA 225-MHz 165BGA

    CY7C1347F

    Abstract: CY7C1347F-200AC CY7C1347F-225AC CY7C1347F-225BGC CY7C1347F-250AC CY7C1347F-250BGC
    Text: CY7C1347F 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache


    Original     		PDF CY7C1347F CY7C1347F 119-Ball CY7C1347F-200AC CY7C1347F-225AC CY7C1347F-225BGC CY7C1347F-250AC CY7C1347F-250BGC

    CY7C1461AV33

    Abstract: CY7C1463AV33 CY7C1465AV33 K1061 u946 B897
    Text: CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 PRELIMINARY 36-Mbit 1M x 36/2 M x 18/512K x 72 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.


    Original     		PDF CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 36-Mbit 18/512K 133-MHz 100-MHz CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 K1061 u946 B897

    CY7C1480V33

    Abstract: CY7C1482V33 CY7C1486V33
    Text: CY7C1480V33 CY7C1482V33 CY7C1486V33 PRELIMINARY 72-Mbit 2M x 36/4M x 18/1M x 72 Pipelined Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200,167 MHz • Registered inputs and outputs for pipelined operation


    Original     		PDF CY7C1480V33 CY7C1482V33 CY7C1486V33 72-Mbit 36/4M 18/1M 250-MHz 200-MHz 167-MHz CY7C1480V33 CY7C1482V33 CY7C1486V33

    CY7C1440V33

    Abstract: No abstract text available
    Text: CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.7, 3.0 and 3.5 ns


    Original     		PDF CY7C1440V33 CY7C1442V33 CY7C1446V33 36/2M 18/512K CY7C1440V33/CY7C1442V33/CY7C1446V33 CY7C1440V33

    CY7C1441AV33

    Abstract: CY7C1443AV33 CY7C1447AV33
    Text: CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common I/O • 3.3V –5% and +10% core power supply (VDD)


    Original     		PDF CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 36-Mbit 36/2M 18/512K 133-MHz CY7C1441AV33 CY7C1443AV33 CY7C1447AV33

    CY7C1440AV33

    Abstract: CY7C1442AV33 CY7C1446AV33
    Text: CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 36-Mbit 1 M x 36/2 M × 18/512 K × 72 Pipelined Sync SRAM 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200 and 167 MHz


    Original     		PDF CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 36-Mbit 250-MHz CY7C1440AV33 CY7C1442AV33 CY7C1446AV33

    Untitled

    Abstract: No abstract text available
    Text: CY7C1481V25 CY7C1483V25 CY7C1487V25 PRELIMINARY 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations • 2M X 36/4M X 18/1M x72 common I/O • 2.5V core power supply (VDD) • 2.5V or 1.8V I/O supply (VDDQ)


    Original     		PDF CY7C1481V25 CY7C1483V25 CY7C1487V25 72-Mbit 36/4M 18/1M 133-MHz

    CY7C1440AV25

    Abstract: CY7C1442AV25 CY7C1446AV25
    Text: CY7C1440AV25 CY7C1442AV25 CY7C1446AV25 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation


    Original     		PDF CY7C1440AV25 CY7C1442AV25 CY7C1446AV25 36-Mbit 36/2M 18/512K 250-MHz CY7C1440AV25, CY7C1442AV25 CY7C1440AV25 CY7C1446AV25

    CY7C1441AV33

    Abstract: CY7C1443AV33 CY7C1447AV33
    Text: CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1M x 36/2M x 18/512K x 72 common IO ■ 3.3V core power supply ■ 2.5V or 3.3V IO power supply


    Original     		PDF CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 36-Mbit 36/2M 18/512K 133-MHz CY7C1441AV33 CY7C1447AV33

    250ac to 30 v ac

    Abstract: CY7C1462V25 CY7C1464V25 CY7C1460V25
    Text: CY7C1460V25 CY7C1462V25 CY7C1464V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns


    Original     		PDF CY7C1460V25 CY7C1462V25 CY7C1464V25 36/2M 18/512K CY7C1460V25 CY7C1462V25 250ac to 30 v ac CY7C1464V25

    CY7C1443V33

    Abstract: CY7C1441V33
    Text: CY7C1441V33 CY7C1443V33 CY7C1447V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-through SRAM Features • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common I/O • Fast clock-to-output times — 6.5 ns for 133-MHz device — 7.5 ns (for 117-MHz device)


    Original     		PDF CY7C1441V33 CY7C1443V33 CY7C1447V33 36/2M 18/512K 133-MHz 117-MHz CY7C1443V33 CY7C1441V33

    CY7C1444V33

    Abstract: No abstract text available
    Text: CY7C1444V33 CY7C1445V33 PRELIMINARY 1M x 36/2M x 18 Pipelined DCD SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.7, 3.0 and 3.5 ns


    Original     		PDF CY7C1444V33 CY7C1445V33 36/2M CY7C1444V33/CY7C1445V33 300-MHz BG119) CY7C1444V33

    Untitled

    Abstract: No abstract text available
    Text: CY7C1441AV33 36-Mbit 1 M x 36 Flow-Through SRAM 36-Mbit (1 M × 36) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36 common I/O ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times


    Original     		PDF CY7C1441AV33 36-Mbit CY7C1441AV33 133-MHz

    cy7c1441av33-133axi

    Abstract: R1136 CY7C1441
    Text: CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 36-Mbit 1 M x 36/2 M × 18/512 K × 72 Flow-Through SRAM 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36/2 M × 18/512 K × 72 common IO


    Original     		PDF CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 36-Mbit CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 133-MHz 727-CY7C1441AV33-133 CY7C1441AV33-133AXI cy7c1441av33-133axi R1136 CY7C1441

    Untitled

    Abstract: No abstract text available
    Text: CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles


    Original     		PDF CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 36-Mbit 36/2M 18/512K 133-MHz 100-MHz

    CY7C1440AV25

    Abstract: CY7C1442AV25 CY7C1446AV25
    Text: CY7C1440AV25 CY7C1442AV25 CY7C1446AV25 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation


    Original     		PDF CY7C1440AV25 CY7C1442AV25 CY7C1446AV25 36-Mbit 36/2M 18/512K 250-MHz CY7C1440AV25, CY7C1442AV25 CY7C1440AV25 CY7C1446AV25